Low-complexity low-density parity check decoding algorithm for high-speed very large scale integration implementation

2012 ◽  
Vol 6 (16) ◽  
pp. 2575-2581 ◽  
Author(s):  
F. Angarita ◽  
J. Marín-Roig ◽  
V. Almenar ◽  
J. Valls
Keyword(s):  
High Speed ◽  
Large Scale ◽  
Low Complexity ◽  
Very Large Scale Integration ◽  
Low Density ◽  
Parity Check ◽  
Decoding Algorithm ◽  
Low Density Parity Check ◽  
Large Scale Integration ◽  
Scale Integration

scholarly journals Design of Quasi-Cyclic Low Density Parity Check Decoder Using Optimized Min-Sum Algorithm

2018 ◽  
Vol 7 (03) ◽  
pp. 23781-23784
Author(s):  
Rajarshini Mishra
Keyword(s):  
Variance Estimation ◽  
Cyclic Codes ◽  
Ldpc Codes ◽  
Ldpc Code ◽  
Low Complexity ◽  
Low Density ◽  
Parity Check ◽  
Decoding Algorithm ◽  
Low Density Parity Check ◽  
Xilinx Fpga

Low-density parity-check (LDPC) have been shown to have good error correcting performance approaching Shannon’s limit. Good error correcting performance enables efficient and reliable communication. However, a LDPC code decoding algorithm needs to be executed efficiently to meet cost , time, power and bandwidth requirements of target applications. Quasi-cyclic low-density parity-check (QC-LDPC) codes are an important subclass of LDPC codes that are known as one of the most effective error controlling methods. Quasi cyclic codes are known to possess some degree of regularity. Many important communication standards such as DVB-S2 and 802.16e use these codes. The proposed Optimized Min-Sum decoding algorithm performs very close to the Sum-Product decoding while preserving the main features of the Min-Sum decoding, that is low complexity and independence with respect to noise variance estimation errors.Proposed decoder is well matched for VLSI implementation and will be implemented on Xilinx FPGA family

scholarly journals Vedic division methodology for high-speed very large scale integration applications

2014 ◽  
Vol 2014 (2) ◽  
pp. 51-59 ◽  
Author(s):  
Prabir Saha ◽  
Deepak Kumar ◽  
Partha Bhattacharyya ◽  
Anup Dandapat
Keyword(s):  
High Speed ◽  
Large Scale ◽  
Very Large Scale Integration ◽  
Large Scale Integration ◽  
Scale Integration
Sign in / Sign up

Export Citation Format

Share Document