An efficient high-speed block turbo code decoding algorithm and hardware architecture design

2004 ◽  
Author(s):  
Kyungchul Yoo ◽  
Hyungshik Shin ◽  
Yunho Jung ◽  
Junghyuck Lee ◽  
Jaeseok Kim
Keyword(s):  
High Speed ◽  
Turbo Code ◽  
Hardware Architecture ◽  
Architecture Design ◽  
Decoding Algorithm ◽  
Block Turbo Code

FAST ALGORITHM ANALYSIS AND BIT-SERIAL ARCHITECTURE DESIGN FOR SUB-PIXEL MOTION ESTIMATION IN H.264

2010 ◽  
Vol 19 (08) ◽  
pp. 1665-1687 ◽  
Author(s):  
MOHAMMAD REZA HOSSEINY FATEMI ◽  
HASAN F. ATES ◽  
ROSLI SALLEH
Keyword(s):  
Motion Estimation ◽  
High Speed ◽  
Reference Frames ◽  
Optimization Techniques ◽  
Algorithm Analysis ◽  
Architecture Design ◽  
Memory Requirement ◽  
Computational Budget ◽  
Bit Serial ◽  
Operation Frequency

The sub-pixel motion estimation (SME), together with the interpolation of reference frames, is a computationally extensive part of the H.264 encoder that increases the memory requirement 16-times for each reference frame. Due to the huge computational complexity and memory requirement of the H.264 SME, its hardware architecture design is an important issue especially in high resolution or low power applications. To solve the above difficulties, we propose several optimization techniques in both algorithm and architecture levels. In the algorithm level, we propose a parabolic based algorithm for SME with quarter-pixel accuracy which reduces the computational budget by 94.35% and the memory access requirement by 98.5% in comparison to the standard interpolate and search method. In addition, a fast version of the proposed algorithm is presented that reduces the computational budget 46.28% further while maintaining the video quality. In the architecture level, we propose a novel bit-serial architecture for our algorithm. Due to advantages of the bit-serial architecture, it has a low gate count, high speed operation frequency, low density interconnection, and a reduced number of I/O pins. Also, several optimization techniques including the sum of absolute differences truncation, source sharing exploiting and power saving techniques are applied to the proposed architecture which reduce power consumption and area. Our design can save between 57.71–90.01% of area cost and improves the macroblock (MB) processing speed between 1.7–8.44 times when compared to previous designs. Implementation results show that our design can support real time HD1080 format with 20.3 k gate counts at the operation frequency of 144.9 MHz.

Sign in / Sign up

Export Citation Format

Share Document