Scan Chain Design Targeting Dual Power and Delay Optimization for 3D Integrated Circuit

2009 ◽  
Author(s):  
Chandan Giri ◽  
Surajit Kumar Roy ◽  
Baishali Banerjee ◽  
Hafizur Rahaman
Keyword(s):  
Integrated Circuit ◽  
Delay Optimization ◽  
Scan Chain ◽  
Scan Chain Design ◽  
Dual Power

Thermal Frequency Imaging: A New Application of Laser Voltage Imaging Applied on 40nm Technology

2011 ◽  
Author(s):  
Guillaume Celi ◽  
Sylvain Dudit ◽  
Thierry Parrassin ◽  
Philippe Perdu ◽  
Antoine Reverdy ◽  
...  
Keyword(s):  
Charge Carrier ◽  
Laser Beam ◽  
Integrated Circuit ◽  
Carrier Density ◽  
Deep Submicron ◽  
Charge Carrier Density ◽  
Voltage Imaging ◽  
A New Technique ◽  
Scan Chain

Abstract For Very Deep submicron Technologies, techniques based on the analysis of reflected laser beam properties are widely used. The Laser Voltage Imaging (LVI) technique, introduced in 2009, allows mapping frequencies through the backside of integrated circuit. In this paper, we propose a new technique based on the LVI technique to debug a scan chain related issue. We describe the method to use LVI, usually dedicated to frequency mapping of digital active parts, in a way that enables localization of resistive leakage. Origin of this signal is investigated on a 40nm case study. This signal can be properly understood when two different effects, charge carrier density variations (LVI) and thermo reflectance effect (Thermal Frequency Imaging, TFI), are taken into account.

scholarly journals Power-scan chain: design for analog testability

2006 ◽  
Author(s):  
A. Zjajo ◽  
Henk Jan Bergveld ◽  
R. Schuttert ◽  
J. Pineda de Gyvez
Keyword(s):  
Scan Chain ◽  
Scan Chain Design

A SAT-Based Pattern Generation Method for Diagnosis Multiple Scan Chain Faults

2011 ◽  
Vol 301-303 ◽  
pp. 989-994
Author(s):  
Fei Wang ◽  
Da Wang ◽  
Hai Gang Yang
Keyword(s):  
Failure Analysis ◽  
Design For Testability ◽  
Pattern Generation ◽  
Diagnostic Process ◽  
High Quality ◽  
Analysis Process ◽  
Short Period ◽  
Multiple Scan ◽  
Scan Chain ◽  
Scan Chain Design

Scan chain design is a widely used design-for-testability (DFT) technique to improve test and diagnosis quality. However, failures on scan chain itself account for up to 30% of chip failures. To diagnose root causes of scan chain failures in a short period is vital to failure analysis process and yield improvements. As the conventional diagnosis process usually runs on the faulty free scan chain, scan chain faults may disable the diagnostic process, leaving large failure area to time-consuming failure analysis. In this paper, a SAT-based technique is proposed to generate patterns to diagnose scan chain faults. The proposed work can efficiently generate high quality diagnostic patterns to achieve high diagnosis resolution. Moreover, the computation overhead of proving equivalent faults is reduced. Experimental results on ISCAS’89 benchmark circuits show that the proposed method can reduce the number of diagnostic patterns while achieving high diagnosis resolution.

Asymmetric Data-Frequency Mapping and Multi Trigger-Probing for Improved Scan Debug

2018 ◽  
Author(s):  
Swaminathan ◽  
Anuradha ◽  
Abuayob ◽  
Eli ◽  
Konstantine Gitelmkher ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Laser Scanning ◽  
Continuous Wave ◽  
Signal To Noise Ratio ◽  
Fault Isolation ◽  
Laser Scanning Microscopy ◽  
Mapping Technique ◽  
Acquisition Time ◽  
Scan Chain ◽  
Continuous Wave Signal

Abstract Integrated-circuit device dimensions continue to shrink, enabling higher density of devices and smaller node size. A number of strategies to improve the resolution of failure analysis and fault isolation tools exist, but some of these techniques are reaching fundamental limits so that engineers are also challenged to innovative methods to increase the useful life of existing toolsets. Laser Scanning Microscopy including Laser Voltage Probing and frequency mapping struggle to maintain resolution commensurate with shrinking feature size. Here we present two methods to improve efficiency and capability of this toolset using existing optical hardware and configuration. The first method applies a frequency mapping technique using scan chain data patterns that allow for data manipulation. This enables an effective resolution increase through deconvolution of data collected in a sequence of scans completed on varied device states. A second method using multiple triggers per loop to evaluate a deterministic continuous wave signal is shown to reduce probe acquisition time, improve job throughput time, and enable, better signal-to-noise ratio for common scan chain debug workflow.

Scan chain design for shift power reduction in scan-based testing

2011 ◽  
Vol 54 (4) ◽  
pp. 767-777
Author(s):  
Jia Li ◽  
Yu Hu ◽  
XiaoWei Li
Keyword(s):  
Power Reduction ◽  
Scan Chain ◽  
Scan Chain Design

Power-Driven Routing-Constrained Scan Chain Design

2004 ◽  
Vol 20 (6) ◽  
pp. 647-660 ◽  
Author(s):  
Y. Bonhomme ◽  
P. Girard ◽  
L. Guiller ◽  
C. Landrault ◽  
S. Pravossoudovitch
Keyword(s):  
Scan Chain ◽  
Scan Chain Design
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