Automatic high-level synthesis of multi-threaded hardware accelerators

2014 ◽  
Author(s):  
Jens Huthmann ◽  
Julian Oppermann ◽  
Andreas Koch
Keyword(s):  
High Level Synthesis ◽  
Hardware Accelerators ◽  
High Level

scholarly journals FPGA-Based Solution for On-Board Verification of Hardware Modules Using HLS

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2024
Author(s):  
Julián Caba ◽  
Fernando Rincón ◽  
Jesús Barba ◽  
José Antonio de la Torre ◽  
Juan Carlos López
Keyword(s):  
Software Industry ◽  
Design Flow ◽  
High Level Synthesis ◽  
Reconfigurable Systems ◽  
Hardware Accelerators ◽  
Testing Environment ◽  
Development Life Cycle ◽  
Verification Process ◽  
Specialized Hardware ◽  
High Level

High-Level Synthesis (HLS) tools provide facilities for the development of specialized hardware accelerators (HWacc). However, the verification stage is still the longest phase in the development life-cycle. Unlike in the software industry, HLS tools lack testing frameworks that could cover the whole design flow, especially the on-board verification stage of the generated RTL. This work introduces a framework for on-board verification of HLS-based modules by using reconfigurable systems and Docker containers with the aim to automate the verification process and preserve a clean testing environment, making the testbed reusable across different stages of the design flow. Moreover, our solution features a mechanism to check timing requirements of the HWacc. We have applied our solution to the C-kernels of the CHStone Benchmark on a Zedboard, in which the on-board verification process has been accelerated up to four times.

scholarly journals Securing Hardware Accelerators: A New Challenge for High-Level Synthesis

2018 ◽  
Vol 10 (3) ◽  
pp. 77-80 ◽  
Author(s):  
Christian Pilato ◽  
Siddharth Garg ◽  
Kaijie Wu ◽  
Ramesh Karri ◽  
Francesco Regazzoni
Keyword(s):  
High Level Synthesis ◽  
Hardware Accelerators ◽  
High Level
Sign in / Sign up

Export Citation Format

Share Document