Power management in high-level synthesis

G. Lakshminarayana; A. Raghunathan; N.K. Jha; S. Dey

doi:10.1109/92.748195

Power management in high-level synthesis

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/92.748195 ◽

1999 ◽

Vol 7 (1) ◽

pp. 7-15 ◽

Cited By ~ 22

Author(s):

G. Lakshminarayana ◽

A. Raghunathan ◽

N.K. Jha ◽

S. Dey

Keyword(s):

Power Management ◽

High Level Synthesis ◽

High Level

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Register binding based power management for high-level synthesis of control-flow intensive behaviors

Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors ◽

10.1109/iccd.2002.1106800 ◽

2003 ◽

Cited By ~ 2

Author(s):

Lin Zhong ◽

Jiong Luo ◽

Yunsi Fei ◽

N.K. Jha

Keyword(s):

Power Management ◽

Control Flow ◽

High Level Synthesis ◽

High Level

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Utilizing Power Management and Timing Slack for Low Power in High-Level Synthesis

2018 IEEE International Conference on Consumer Electronics-Taiwan (ICCE-TW) ◽

10.1109/icce-china.2018.8448584 ◽

2018 ◽

Author(s):

Zong-Han Xie ◽

Shih-Hsu Huang ◽

Chun-Hua Cheng

Keyword(s):

Low Power ◽

Power Management ◽

High Level Synthesis ◽

High Level

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PMHLS 2.0: An automated optimization of power management during high-level synthesis

2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) ◽

10.1109/patmos.2016.7833689 ◽

2016 ◽

Cited By ~ 1

Author(s):

Dominik Macko

Keyword(s):

Power Management ◽

High Level Synthesis ◽

High Level ◽

Automated Optimization

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Transient power management through high level synthesis

IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281) ◽

10.1109/iccad.2001.968703 ◽

2002 ◽

Cited By ~ 12

Author(s):

V. Raghunathan ◽

S. Ravi ◽

A. Raghunathan ◽

G. Lakshminarayana

Keyword(s):

Power Management ◽

High Level Synthesis ◽

High Level

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Adopting High-level Synthesis Approach to Accelerate Power Management Design

2018 7th International Conference on Reliability, Infocom Technologies and Optimization (Trends and Future Directions) (ICRITO) ◽

10.1109/icrito.2018.8748268 ◽

2018 ◽

Author(s):

Katarina Jelemenska ◽

Dominik Macko

Keyword(s):

Power Management ◽

High Level Synthesis ◽

High Level ◽

Synthesis Approach

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Power-management high-level synthesis

2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) ◽

10.1109/vlsi-soc.2015.7314393 ◽

2015 ◽

Cited By ~ 7

Author(s):

Dominik Macko ◽

Katarina Jelemenska ◽

Pavel Cicak

Keyword(s):

Power Management ◽

High Level Synthesis ◽

High Level

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A power management methodology for high-level synthesis

Proceedings Eleventh International Conference on VLSI Design ◽

10.1109/icvd.1998.646573 ◽

2002 ◽

Cited By ~ 8

Author(s):

G. Lakshminarayana ◽

A. Raghunathan ◽

N.K. Jha ◽

S. Dey

Keyword(s):

Power Management ◽

High Level Synthesis ◽

High Level

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Simultaneous functional units and register allocation based power management for high-level synthesis of data-intensive applications

2010 International Conference on Communications, Circuits and Systems (ICCCAS) ◽

10.1109/icccas.2010.5581860 ◽

2010 ◽

Author(s):

Feng Wu ◽

Ning Xu ◽

Fei Zheng ◽

Fubing Mao

Keyword(s):

Power Management ◽

High Level Synthesis ◽

Data Intensive ◽

Functional Units ◽

High Level ◽

Data Intensive Applications

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Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e92.a.3169 ◽

2009 ◽

Vol E92-A (12) ◽

pp. 3169-3179 ◽

Cited By ~ 7

Author(s):

Akira OHCHI ◽

Nozomu TOGAWA ◽

Masao YANAGISAWA ◽

Tatsuo OHTSUKI

Keyword(s):

High Level Synthesis ◽

High Level

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A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e100.a.1439 ◽

2017 ◽

Vol E100.A (7) ◽

pp. 1439-1451

Author(s):

Koki IGAWA ◽

Masao YANAGISAWA ◽

Nozomu TOGAWA

Keyword(s):

High Level Synthesis ◽

Synthesis Algorithm ◽

Body Biasing ◽

High Level ◽

Delay Variation

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