2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
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9781467391405

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Trace Buffer Attack: Security versus observability study in post-silicon debug

2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) ◽

10.1109/vlsi-soc.2015.7314443 ◽

2015 ◽

Cited By ~ 9

Author(s):

Yuanwen Huang ◽

Anupam Chattopadhyay ◽

Prabhat Mishra

Keyword(s):

Silicon Debug

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External reviewers

2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) ◽

10.1109/vlsi-soc.2015.7314380 ◽

2015 ◽

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Locality-aware vertex scheduling for GPU-based graph computation

2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) ◽

10.1109/vlsi-soc.2015.7314415 ◽

2015 ◽

Cited By ~ 2

Author(s):

Hyunsun Park ◽

Junwhan Ahn ◽

Eunhyeok Park ◽

Sungjoo Yoo

Keyword(s):

Graph Computation

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Keynote presentations

2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) ◽

10.1109/vlsi-soc.2015.7314381 ◽

2015 ◽

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Analysis and testing on delays with two time frames

2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) ◽

10.1109/vlsi-soc.2015.7314384 ◽

2015 ◽

Author(s):

Masahiro Fujita

Keyword(s):

Time Frames

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Design of asynchronous RISC CPU register-file Write-Back queue

2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) ◽

10.1109/vlsi-soc.2015.7314387 ◽

2015 ◽

Cited By ~ 1

Author(s):

Matthew M. Kim ◽

Karl M. Fant ◽

Paul Beckett

Keyword(s):

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Traffic-aware buffer reconfiguration in on-chip networks

2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) ◽

10.1109/vlsi-soc.2015.7314416 ◽

2015 ◽

Author(s):

Ramin Bashizade ◽

Hamid Sarbazi-Azad

Keyword(s):

On Chip

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On the estimation of assertion interestingness

2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) ◽

10.1109/vlsi-soc.2015.7314438 ◽

2015 ◽

Cited By ~ 10

Author(s):

Tara Ghasempouri ◽

Graziano Pravadelli

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Design optimization of polyphase digital down converters for extremely high frequency wireless communications

2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) ◽

10.1109/vlsi-soc.2015.7314417 ◽

2015 ◽

Cited By ~ 2

Author(s):

Gain Kim ◽

Raffaele Capoccia ◽

Yusuf Leblebici

Keyword(s):

Wireless Communications ◽

Design Optimization ◽

High Frequency ◽

Extremely High Frequency

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2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) ◽

10.1109/vlsi-soc.2015.7314375 ◽

2015 ◽

Download Full-text

2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Trace Buffer Attack: Security versus observability study in post-silicon debug

External reviewers

Locality-aware vertex scheduling for GPU-based graph computation

Keynote presentations

Analysis and testing on delays with two time frames

Design of asynchronous RISC CPU register-file Write-Back queue

Traffic-aware buffer reconfiguration in on-chip networks

On the estimation of assertion interestingness

Design optimization of polyphase digital down converters for extremely high frequency wireless communications

Table of contents

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2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Trace Buffer Attack: Security versus observability study in post-silicon debug

External reviewers

Locality-aware vertex scheduling for GPU-based graph computation

Keynote presentations

Analysis and testing on delays with two time frames

Design of asynchronous RISC CPU register-file Write-Back queue

Traffic-aware buffer reconfiguration in on-chip networks

On the estimation of assertion interestingness

Design optimization of polyphase digital down converters for extremely high frequency wireless communications

Table of contents

2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
Latest Publications