Automated pin grid array package routing on multilayer ceramic substrates

1993 ◽  
Vol 1 (4) ◽  
pp. 571-575 ◽  
Author(s):  
C. Ying ◽  
J. Gu
Keyword(s):  
Ceramic Substrates ◽  
Multilayer Ceramic

Mechanical strength enhancement of low temperature co-fired multilayer ceramic substrates by introducing residual stress

2019 ◽  
Vol 45 (8) ◽  
pp. 10982-10990 ◽  
Author(s):  
Suxiang Qian ◽  
Feng Liu ◽  
Mingsheng Ma ◽  
Guanyu Chen ◽  
Zhifu Liu ◽  
...  
Keyword(s):  
Residual Stress ◽  
Low Temperature ◽  
Mechanical Strength ◽  
Ceramic Substrates ◽  
Strength Enhancement ◽  
Multilayer Ceramic

The Direct plating copper (DPC) ceramic material on Al2O3/AlN or LTCC (Low-temperature co-fired ceramic) substrates

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 001773-001790
Author(s):  
Ho-Chieh (Jay) Yu ◽  
Jason Huang
Keyword(s):  
Electrical Resistance ◽  
Ceramic Substrate ◽  
Conducting Material ◽  
Ceramic Substrates ◽  
Direct Plating ◽  
Key Technology ◽  
Metal Trace ◽  
Metal Ceramic ◽  
Via Holes ◽  
Multilayer Ceramic

RESEARCH BACKGROUND: The now used ceramic substrate or sub-mounted are normally based on Ag-printed, direct bonding copper (DBC) ceramic or LTCC (Low temperature co-fired ceramic)/HTCC (High temperature co-fired ceramic) technology.Due to the limit of the screen-printed process, the resolution and conducting material thickness the Ag-printed, LTCC and HTCC substrate are poor. The poor resolutions make these materials difficult to use in high density and flip-chip device design. And the related thinner conducting material (normally <20um) limits the power rating of the design.DBC is now widely applied in power circuit design, however, duo to the copper lamination process requirement, more than 300um in thickness of copper layer is needed. Any lower copper thickness design should have an extra costly grind to reach. Also, the DBC material is difficult to provide to the multilayer trace design. OUR GOAL: We want to provide a solution with multilayer ceramic substrate for high power and high device density applications. Besides, the material properties, the adhesion of the metal/ceramic also be considered. Following are the material characteristics required for the development:A low electrical resistance material: Copper.A thick trace material thickness of more than 3 oz.A high thermal conductivity and stability ceramics with via-holes for TSV plating (Drilled Al2O3/AlN substrate ) or non- shrinking LTCC materialHigh metal trace resolution whose line width and space could be only 50 umWell metal/ceramic adhesion uniformity and strength is required: The voids between metal/ceramic < 1%; The adhesion strength> 2 kg/2*2mm2. METHODS & RESULTS: Metal trace plating: For high resolution and lower material electrical resistance request of the trace metal, we introduce electrical casting direct-plating copper (DPC) technology. The first copper is sputtered on the ceramic substrate using Ti as combined/buffer layer between copper and ceramic to provide good adhesion strength and stability. The second copper is made by electrical casting process to increase its thickness to 3 to 5 oz. (100~150um). The key technology of the metal trace plating is the material control of the sputter layers and the second copper layer stress release during plating. Multilayer Ceramic substrates: For double layers design, we use sintered Al2O3 or AlN substrates with electrical conducting via-holes design. The via-holes are made by laser drilling. And the conducting of the front and back side is connected by the following plating process. The key technology of this process is the stability of the via-holes. We have to make sure the via-holes cleaning, impurity removing and material variation during high temperature laser drilled is well controlled. For the more than three layers design, the non-shrinking LTCC is used. The dimension mismatch of the non-shrinking LTCC can controlled less than 100um., much better than that of normal LTCC/HTCC. By the correction of the following DPC process, the tolerance of the metal trace can be controlled < 30 um. The key technology of this process is the non-shrinking LTCC technology and the adhesion of the DPC metal on LTCC material.

Microstructural and Electrical Characterization of Barium Strontium Titanatebased Solid Solution Thin Films Deposited on Ceramic Substrates by Pulsed Laser Deposition

2002 ◽  
Vol 720 ◽  
Author(s):  
Costas G. Fountzoulas ◽  
Daniel M. Potrepka ◽  
Steven C. Tidrow
Keyword(s):  
Thin Films ◽  
Dielectric Constant ◽  
Pulsed Laser Deposition ◽  
Pulsed Laser ◽  
Electrical Characterization ◽  
Field Variable ◽  
Laser Deposition ◽  
X Ray Diffraction ◽  
Ceramic Substrates ◽  
Nominal Thickness

AbstractFerroelectrics are multicomponent materials with a wealth of interesting and useful properties, such as piezoelectricity. The dielectric constant of the BSTO ferroelectrics can be changed by applying an electric field. Variable dielectric constant results in a change in phase velocity in the device allowing it to be tuned in real time for a particular application. The microstructure of the film influences the electronic properties which in turn influences the performance of the film. Ba0.6Sr0.4Ti1-y(A 3+, B5+)yO3 thin films, of nominal thickness of 0.65 μm, were synthesized initially at substrate temperatures of 400°C, and subsequently annealed to 750°C, on LaAlO3 (100) substrates, previously coated with LaSrCoO conductive buffer layer, using the pulsed laser deposition technique. The microstructural and physical characteristics of the postannealed thin films have been studied using x-ray diffraction, scanning electron microscopy, and nano indentation and are reported. Results of capacitance measurements are used to obtain dielectric constant and tunability in the paraelectric (T>Tc) regime.

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