The Direct plating copper (DPC) ceramic material on Al2O3/AlN or LTCC (Low-temperature co-fired ceramic) substrates

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 001773-001790
Author(s):  
Ho-Chieh (Jay) Yu ◽  
Jason Huang
Keyword(s):  
Electrical Resistance ◽  
Ceramic Substrate ◽  
Conducting Material ◽  
Ceramic Substrates ◽  
Direct Plating ◽  
Key Technology ◽  
Metal Trace ◽  
Metal Ceramic ◽  
Via Holes ◽  
Multilayer Ceramic

RESEARCH BACKGROUND: The now used ceramic substrate or sub-mounted are normally based on Ag-printed, direct bonding copper (DBC) ceramic or LTCC (Low temperature co-fired ceramic)/HTCC (High temperature co-fired ceramic) technology.Due to the limit of the screen-printed process, the resolution and conducting material thickness the Ag-printed, LTCC and HTCC substrate are poor. The poor resolutions make these materials difficult to use in high density and flip-chip device design. And the related thinner conducting material (normally <20um) limits the power rating of the design.DBC is now widely applied in power circuit design, however, duo to the copper lamination process requirement, more than 300um in thickness of copper layer is needed. Any lower copper thickness design should have an extra costly grind to reach. Also, the DBC material is difficult to provide to the multilayer trace design. OUR GOAL: We want to provide a solution with multilayer ceramic substrate for high power and high device density applications. Besides, the material properties, the adhesion of the metal/ceramic also be considered. Following are the material characteristics required for the development:A low electrical resistance material: Copper.A thick trace material thickness of more than 3 oz.A high thermal conductivity and stability ceramics with via-holes for TSV plating (Drilled Al2O3/AlN substrate ) or non- shrinking LTCC materialHigh metal trace resolution whose line width and space could be only 50 umWell metal/ceramic adhesion uniformity and strength is required: The voids between metal/ceramic < 1%; The adhesion strength> 2 kg/2*2mm2. METHODS & RESULTS: Metal trace plating: For high resolution and lower material electrical resistance request of the trace metal, we introduce electrical casting direct-plating copper (DPC) technology. The first copper is sputtered on the ceramic substrate using Ti as combined/buffer layer between copper and ceramic to provide good adhesion strength and stability. The second copper is made by electrical casting process to increase its thickness to 3 to 5 oz. (100~150um). The key technology of the metal trace plating is the material control of the sputter layers and the second copper layer stress release during plating. Multilayer Ceramic substrates: For double layers design, we use sintered Al2O3 or AlN substrates with electrical conducting via-holes design. The via-holes are made by laser drilling. And the conducting of the front and back side is connected by the following plating process. The key technology of this process is the stability of the via-holes. We have to make sure the via-holes cleaning, impurity removing and material variation during high temperature laser drilled is well controlled. For the more than three layers design, the non-shrinking LTCC is used. The dimension mismatch of the non-shrinking LTCC can controlled less than 100um., much better than that of normal LTCC/HTCC. By the correction of the following DPC process, the tolerance of the metal trace can be controlled < 30 um. The key technology of this process is the non-shrinking LTCC technology and the adhesion of the DPC metal on LTCC material.

Investigation of the Direct Plating Copper (DPC) on Al2O3, BeO or AlN Ceramic Substrates for High Power Density Applications

2016 ◽  
Vol 2016 (1) ◽  
pp. 000079-000086 ◽  
Author(s):  
Ho-Chieh (Jay) Yu ◽  
Jason Huang
Keyword(s):  
Power Density ◽  
High Power ◽  
Substrate Material ◽  
Ceramic Substrate ◽  
High Power Density ◽  
Power Module ◽  
Ceramic Substrates ◽  
Metal Ceramic ◽  
Via Holes ◽  
Pattern Resolution

Abstract In the high power module applications, the power increasing and the size shrinking becomes one of the major topics for the power module design. Due to both the power increasing and the size decreasing, the power density of the device will be much increased. Therefore, not only the thermal conductivity and stability of the substrate material but the long-term material reliability of the substrate have to be seriously considered. For these reasons, the ceramic PCB becomes one of the best solutions. The ceramic substrates now used are normally based on Ag-printed or direct bonding copper (DBC) technology. In the case of the Ag-printed ceramic substrate, the pattern resolution and metallization thickness are limited by the Ag-printed process. Also the combination strength of the silver and ceramic substrate by glass (which is normally mixed in the silver paste) is normally not good enough. A thermal dissipation barrier will then be formed between silver and ceramic substrate due to the poor thermal conductivity of the glass material. For the DBC ceramic substrate, DBC substrates are manufactured at 1065°C by the diffusion between ceramic and Cu/CuO layer. A thicker Cu layer thickness of normally more than 300 um is required in the thermal compressing bonding process. The Cu pattern resolution will then be limited by the thickness of the Cu layer. However, the about 5~10% of the voids exist randomly between ceramic and Cu layer is the other major issue. The resolution issues of the Ag-printed and DBC ceramic substrates make the limitation for the device density design (fine line/width and flip-chip device design become very difficult). The glass material in the Ag printed ceramic substrate and the 5~10% voids existence in DBC ceramic substrate may cause the reliability issue operating at a high power density applications. For high power density module applications, we introduce the DPC technology on the ceramic substrate. In DPC ceramic substrate system, the sputtered Ti is used as the combination material between Cu and ceramic substrate. And the first copper is then sputtered on the top of Ti layer as seed-layer for the following Cu electrode plating (second cupper layer). By the material and the sputtering process control, several ceramic substrate raw materials can be used, such as Al2O3, AlN, BeO, Si3N4 and so on. The Ti combined/buffer layer provides good adhesion strength and material stability. The second copper layer is plated by electrode casting plating to 3 to 5 oz. (100~150um) in thickness. The key technology of the metal trace plating is the material control of the sputter layers and the second copper layer stress release during plating. In the DPC system, the double layers design is available. The laser drilled via holes on the various ceramic substrates is introduced. The conducting of the front and back side is connected by the following plating process. The key technology of this process is the stability of the via-holes. We have to make sure the via-holes cleaning, impurity removing and material stability during high temperature laser drilled is well controlled. DPC ceramic substrates provide a better metal/ceramic interface uniformity and material reliability due to the stable Ti combination material and much less voids in the metal/ceramic interface. Also, the DPC ceramic substrates provide a gold pattern resolution of 50 um line space with tight tolerance of 20 um min. We believe the material characteristic make DPC a very suitable substrate material for high power module applications.

Root Cause Analysis of a Connector Time-Delayed Fracture

2015 ◽  
Author(s):  
Prabjit Singh ◽  
Ying Yu ◽  
Robert E. Davis
Keyword(s):  
Printed Circuit Board ◽  
Ceramic Substrate ◽  
Circuit Board ◽  
Delayed Fracture ◽  
Ceramic Substrates ◽  
Printed Circuit ◽  
Root Cause ◽  
Chip Carrier ◽  
Electrical Connections ◽  
Grain Boundary Grooves

Abstract A land-grid array connector, electrically connecting an array of plated contact pads on a ceramic substrate chip carrier to plated contact pads on a printed circuit board (PCB), failed in a year after assembly due to time-delayed fracture of multiple C-shaped spring connectors. The land-grid-array connectors analyzed had arrays of connectors consisting of gold on nickel plated Be-Cu C-shaped springs in compression that made electrical connections between the pads on the ceramic substrates and the PCBs. Metallography, fractography and surface analyses revealed the root cause of the C-spring connector fracture to be plating solutions trapped in deep grain boundary grooves etched into the C-spring connectors during the pre-plating cleaning operation. The stress necessary for the stress corrosion cracking mechanism was provided by the C-spring connectors, in the land-grid array, being compressed between the ceramic substrate and the printed circuit board.

Multilayer Ferrite Inductor Substrate for Ceramic-Based High Current Point-of-Load (POL) Converter

2016 ◽  
Vol 2016 (CICMT) ◽  
pp. 000039-000046
Author(s):  
Wenli Zhang ◽  
Yipeng Su ◽  
Fred C. Lee
Keyword(s):  
Low Temperature ◽  
Power Electronics ◽  
Coefficient Of Thermal Expansion ◽  
Ceramic Substrate ◽  
Thermal Interface Material ◽  
Sintering Behavior ◽  
High Current ◽  
Output Current ◽  
Zn Ferrite ◽  
Multilayer Ceramic

Abstract High power-density and high efficiency are the two driving forces for point-of-load (POL) converters used in portable electronics and other applications where system miniaturization is required. Discrete passive components, especially bulky inductors, have become the bottleneck for downsizing POL converters. Low-temperature sintered Ni-Cu-Zn ferrite tapes for multilayer chip inductors have been widely studied and used in high-frequency power electronics applications. In our previous study, a low-profile, planar inductor substrate with lateral flux pattern was fabricated using mixed commercial low-fire Ni-Cu-Zn ferrite tapes and compatible low temperature co-fired ceramic (LTCC) processing. However, thermal interface material was used between active circuit board and passive layer (ferrite substrate), which increases the total volume of the converter and becomes a potential threat for reliability due to the mismatch of coefficient of thermal expansion among different layers. Additionally, this hybrid integration method requires labor-intensive manual steps which are not compatible with cost-sensitive power electronics market. A fully ceramic-based POL module with integrated multilayer ferrite inductor has been proposed. The circuit and other components are designed to be directly built on top of the multilayer ferrite inductor substrate. This presented work focuses on the development of the multilayer ceramic substrate with embedded planar, lateral-flux inductor by co-firing of ferrite and dielectric tapes with conductor paste. Commercial dielectric LTCC and ferrite tapes were chosen for the fabrication of multilayer ferrite inductor substrate. Different silver pastes were co-fired with ceramic tapes to form the inductor winding. The sintering behavior and compatibility of dielectric, magnetic, and conductive components in one co-firing process was studied in order to realize a cohesive multilayer ceramic substrate. The embedded inductors present lower inductance than pure ferrite inductors sintered alone using the same profile when the output current is smaller than 10 A. The inductance of both types of inductors are very similar when output current is above 15 A. The inductor embedded in dielectric tapes exhibits higher core loss density than its counterpart. Future work will focus on the integration of high current POL module using this developed multilayer ferrite inductor substrate.

Studies of composite catalysts of nickel on metal-ceramic substrates

1991 ◽  
Vol 43 (2) ◽  
pp. 545-552 ◽  
Author(s):  
L. L. Kuznetsova ◽  
V. N. Ananin ◽  
A. V. Pashis ◽  
V. V. Belyaev
Keyword(s):  
Ceramic Substrates ◽  
Composite Catalysts ◽  
Metal Ceramic
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