Charge sharing problems in dynamic logic circuits: BiCMOS versus CMOS and a 1.5 V BiCMOS dynamic logic circuit free from charge sharing problems

1995 ◽  
Vol 42 (11) ◽  
pp. 974-977 ◽  
Author(s):  
J.B. Kuo ◽  
C.S. Chiang
Keyword(s):  
Dynamic Logic ◽  
Logic Circuits ◽  
Logic Circuit ◽  
Charge Sharing

scholarly journals A New Model of Dynamic Logic Circuit with NMOS based Keeper

2020 ◽  
Vol 12 (1) ◽  
pp. 1-14
Author(s):  
Riazul Islam ◽  
Satyendra N. Biswas
Keyword(s):  
Dynamic Logic ◽  
Logic Circuits ◽  
Logic Circuit ◽  
New Model ◽  
Comparative Results

AbstractDynamic logic circuits are widely popular due to a smaller number of transistors and consume less area. But the time to switch between logics is higher due to higher contention value. A new model of the logic using nMOS based keeper circuit is proposed and the performance is evaluated using Cadence tools. Comparative results demonstrate the suitability and competency of the proposed circuit.

Low Power Wide Fan-in Domino OR Gate Using CN-MOSFETs

2020 ◽  
Vol 10 (1) ◽  
pp. 55-62
Author(s):  
Deepika Bansal ◽  
Bal Chand Nagar ◽  
Brahamdeo Prasad Singh ◽  
Ajay Kumar
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Dynamic Logic ◽  
Clock Frequency ◽  
Charge Sharing ◽  
Benchmark Circuit ◽  
Domino Circuit ◽  
Power Delay Product ◽  
Domino Circuits ◽  
Or Gate

Background & Objective: In this paper, a modified pseudo domino configuration has been proposed to improve the leakage power consumption and Power Delay Product (PDP) of dynamic logic using Carbon Nanotube MOSFETs (CN-MOSFETs). The simulations for proposed and published domino circuits are verified by using Synopsys HSPICE simulator with 32nm CN-MOSFET technology which is provided by Stanford. Methods: The simulation results of the proposed technique are validated for improvement of wide fan-in domino OR gate as a benchmark circuit at 500 MHz clock frequency. Results: The proposed configuration is suitable for cascading of the high performance wide fan-in circuits without any charge sharing. Conclusion: The performance analysis of 8-input OR gate demonstrate that the proposed circuit provides lower static and dynamic power consumption up to 62 and 40% respectively, and PDP improvement is 60% as compared to standard domino circuit.

scholarly journals Three-dimensional lattice logic circuits, Part I: Fundamentals

2005 ◽  
Vol 18 (1) ◽  
pp. 1-13 ◽  
Author(s):  
Anas Al-Rabadi
Keyword(s):  
Circuit Design ◽  
Fault Localization ◽  
Three Dimensional ◽  
Logic Circuits ◽  
Logic Circuit ◽  
Device Performance ◽  
Important Class ◽  
Future Directions ◽  
Dimensional Lattice ◽  
Current Technology

Fundamentals of regular three-dimensional (3D) lattice circuits are introduced. Lattice circuits represent an important class of regular circuits that allow for local interconnections, predictable timing, fault localization, and self-repair. In addition, three-dimensional lattice circuits can be potentially well suited for future 3D technologies, such as nanotechnologies, where the intrinsic physical delay of the irregular and lengthy interconnections limits the device performance. Although the current technology does not offer a menu for the immediate physical implementation of the proposed three-dimensional circuits, this paper deals with three-dimensional logic circuit design from a fundamental and foundational level for a rather new possible future directions in designing digital logic circuits.

scholarly journals On self-correcting logic circuits of unreliable gates

2021 ◽  
pp. 1-18
Author(s):  
Kirill Andreevich Popkov
Keyword(s):  
Positive Integer ◽  
Boolean Function ◽  
Boolean Functions ◽  
Arbitrary Number ◽  
Logic Circuits ◽  
Logic Circuit ◽  
Complete Basis

The following statements are proved: 1) for any integer m ≥ 3 there is a basis consisting of Boolean functions of no more than m variables, in which any Boolean function can be implemented by a logic circuit of unreliable gates that self-corrects relative to certain faults in an arbitrary number of gates; 2) for any positive integer k there are bases consisting of Boolean functions of no more than two variables, in each of which any Boolean function can be implemented by a logic circuit of unreliable gates that self-correct relative to certain faults in no more than k gates; 3) there is a functionally complete basis consisting of Boolean functions of no more than two variables, in which almost no Boolean function can be implemented by a logic circuit of unreliable gates that self-correct relative to at least some faults in no more than one gate.

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