A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5-V full-swing BiCMOS dynamic logic circuit

J.B. Kuo; K.W. Su; J.H. Lou

doi:10.1109/4.400440

A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5-V full-swing BiCMOS dynamic logic circuit

IEEE Journal of Solid-State Circuits ◽

10.1109/4.400440 ◽

1995 ◽

Vol 30 (8) ◽

pp. 950-954 ◽

Cited By ~ 1

Author(s):

J.B. Kuo ◽

K.W. Su ◽

J.H. Lou

Keyword(s):

Dynamic Logic ◽

Logic Circuit ◽

Wallace Tree ◽

Full Swing

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A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5 V full-swing BiCMOS dynamic logic circuit

Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94 ◽

10.1109/iscas.1994.409262 ◽

2002 ◽

Cited By ~ 1

Author(s):

J.B. Kuo ◽

K.W. Su ◽

J.H. Lou

Keyword(s):

Dynamic Logic ◽

Logic Circuit ◽

Wallace Tree ◽

Full Swing

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Low-power comparator design based on CMOS dynamic logic circuit

2014 2nd International Conference on Emerging Technology Trends in Electronics, Communication and Networking ◽

10.1109/et2ecn.2014.7044932 ◽

2014 ◽

Cited By ~ 1

Author(s):

Chandrahash Patel ◽

C. S. Veena

Keyword(s):

Low Power ◽

Dynamic Logic ◽

Logic Circuit

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An analytical transient model for a 1.5 V BiCMOS dynamic logic circuit for low-voltage deep submicrometer BiCMOS VLSI

IEEE Transactions on Electron Devices ◽

10.1109/16.368053 ◽

1995 ◽

Vol 42 (3) ◽

pp. 549-554 ◽

Cited By ~ 1

Author(s):

C.S. Chiang ◽

J.B. Kuo

Keyword(s):

Low Voltage ◽

Dynamic Logic ◽

Logic Circuit ◽

Transient Model ◽

Deep Submicrometer

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Charge sharing problems in dynamic logic circuits: BiCMOS versus CMOS and a 1.5 V BiCMOS dynamic logic circuit free from charge sharing problems

IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications ◽

10.1109/81.477211 ◽

1995 ◽

Vol 42 (11) ◽

pp. 974-977 ◽

Cited By ~ 5

Author(s):

J.B. Kuo ◽

C.S. Chiang

Keyword(s):

Dynamic Logic ◽

Logic Circuits ◽

Logic Circuit ◽

Charge Sharing

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A novel full-swing low-voltage BiCMOS logic circuit

10.1109/icasic.1996.562826 ◽

2002 ◽

Author(s):

Zhang Qiushuang ◽

Qiu Yulin ◽

Zeng Zhihong

Keyword(s):

Low Voltage ◽

Logic Circuit ◽

Full Swing

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Low-noise and power dynamic logic circuit design based on semi-dynamic buffer

2008 2nd International Conference on Anti-counterfeiting, Security and Identification ◽

10.1109/iwasid.2008.4688424 ◽

2008 ◽

Cited By ~ 9

Author(s):

Fang Tang ◽

Ke Zhu ◽

Quan Gan ◽

JianGuo Tang

Keyword(s):

Circuit Design ◽

Dynamic Logic ◽

Low Noise ◽

Logic Circuit ◽

Power Dynamic

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A 1.5-V full-swing BiCMOS logic circuit

IEEE Journal of Solid-State Circuits ◽

10.1109/4.165337 ◽

1992 ◽

Vol 27 (11) ◽

pp. 1568-1574 ◽

Cited By ~ 41

Author(s):

M. Hiraki ◽

K. Uano ◽

M. Minami ◽

K. Sato ◽

N. Matsuzaki ◽

...

Keyword(s):

Logic Circuit ◽

Full Swing

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A 1.5 V full-swing BiCMOS logic circuit

1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers ◽

10.1109/isscc.1992.200404 ◽

2003 ◽

Cited By ~ 3

Author(s):

M. Hiraki ◽

K. Yano ◽

M. Minami ◽

K. Satoh ◽

N. Matsuzaki ◽

...

Keyword(s):

Logic Circuit ◽

Full Swing

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Novel sub-1V CMOS domino dynamic logic circuit using a direct bootstrap (DB) technique for low-voltage CMOS VLSI

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03. ◽

10.1109/iscas.2003.1206310 ◽

2003 ◽

Author(s):

P.C. Chen ◽

J.B. Kuo

Keyword(s):

Low Voltage ◽

Dynamic Logic ◽

Logic Circuit ◽

Cmos Vlsi

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A dynamic logic circuit embedded flip-flop for ASIC design

Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434) ◽

10.1109/apasic.2000.896898 ◽

2002 ◽

Author(s):

K. Hirairi ◽

H. Kosaka ◽

K. Moriki ◽

K. Keino ◽

K. Onuma

Keyword(s):

Dynamic Logic ◽

Logic Circuit ◽

Flip Flop ◽

Asic Design

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