Permutation realizability and fault tolerance property of the inside-out routing algorithm

1999 ◽  
Vol 10 (9) ◽  
pp. 946-957 ◽  
Author(s):  
Seung-Woo Seo ◽  
Tse-Yun Feng ◽  
Hyoung-Ll Lee
Keyword(s):  
Fault Tolerance ◽  
Routing Algorithm ◽  
Inside Out

FAULT-TOLERANT COMMUNICATIONS ON HYPERCUBE-CLUSTERS

2000 ◽  
Vol 01 (04) ◽  
pp. 315-329 ◽  
Author(s):  
PETER KOK KEONG LOH ◽  
WEN JING HSU
Keyword(s):  
Fault Tolerance ◽  
Interconnection Networks ◽  
Fault Tolerant ◽  
Routing Algorithm ◽  
Cost Effective ◽  
Hardware Support ◽  
Tolerance Level ◽  
Component Faults ◽  
Message Overhead ◽  
Standard Components

Hierarchical interconnection networks with n-dimensional hypercube clusters can strike a balance between wide application suitability, size scalability as well as reliability. Cluster communications support for such networks must therefore be reliable and efficient without incurring large overheads. This paper proposes a reliable and cost-effective intra-cluster communications strategy for such a class of interconnection networks. The routing algorithm can tolerate up to (n - 1) component faults in the cluster and generates routes that are cycle-free and livelock-free. The message is guaranteed to be optimally (respectively, sub-optimally) delivered within a maximum of n (respectively, 2n - 1) hops. The message overhead incurred is one of the lowest reported for the specified fault tolerance level – with only a single n-bit routing vector accompanying the message to be communicated. Finally, routing hardware support may be simply achieved with standard components, facilitating integration with the host network.

Double Stairs: A Fault-Tolerant Routing Algorithm for Networks-on-Chip

2016 ◽  
Vol 25 (06) ◽  
pp. 1650065 ◽  
Author(s):  
Saleh Fakhrali ◽  
Hamid R. Zarandi
Keyword(s):  
Fault Tolerance ◽  
Fault Tolerant ◽  
Routing Algorithm ◽  
Deep Submicron ◽  
Routing Algorithms ◽  
Experimental Results ◽  
Trade Off ◽  
Networks On Chip ◽  
On Chip ◽  
Probabilistic Flooding

Reliability is one of the main concerns in the design of networks-on-chip (NoCs) due to the use of deep submicron technologies in fabrication of such products. This paper presents a new fault-tolerant routing algorithm called double stairs for NoCs. Double stairs routing algorithm is a low overhead routing that has the ability to deal with fault. The proposed routing algorithm makes a redundant copy of each packet at the source node and routes the original and redundant packets in a new partially adaptive routing algorithm. The method is evaluated for various packet injection rates and fault rates. Experimental results show that the proposed routing algorithm offers the best trade-off between performance and fault tolerance compared to other routing algorithms, namely flooding, XYX and probabilistic flooding.

scholarly journals Multipath Routing Based on Genetic Algorithm in Wireless Sensor Networks

2021 ◽  
Vol 2021 ◽  
pp. 1-6
Author(s):  
Shuang Wang
Keyword(s):  
Genetic Algorithm ◽  
Wireless Sensor Networks ◽  
Fault Tolerance ◽  
Sensor Networks ◽  
Fitness Function ◽  
Routing Algorithm ◽  
Multipath Routing ◽  
Base Station ◽  
Wireless Sensor ◽  
Routing Scheme

The two most important factors that must be considered in the wireless sensor networks are energy efficiency and fault tolerance. Multipath routing is an effective method to improve the fault tolerance in wireless sensor networks. By taking the energy consumption into consideration, in this paper, a multipath routing algorithm for the wireless sensor networks based on the genetic algorithm is proposed. The proposed algorithm computes the fitness function by using the distance between nodes in the network and then generates the routing scheme at the base station. The routing scheme is shared with all the nodes of the entire network, to realize the multipath routing for each node. Finally, the simulation experiment is used to verify the validity of our method, and the results show that the routing method in this paper has a better effect.

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