The reconfigurable fault tolerance routing algorithm in mesh topology structure

2014 ◽  
Author(s):  
Jianfei Wu ◽  
Hua Cai ◽  
Fuheng Qu ◽  
Yong Yang
Keyword(s):  
Fault Tolerance ◽  
Routing Algorithm ◽  
Topology Structure ◽  
Mesh Topology

scholarly journals Level Based Routing Using Dynamic Programming for 2D Mesh

2017 ◽  
Vol 17 (2) ◽  
pp. 73-82 ◽  
Author(s):  
Akash Punhani ◽  
Pardeep Kumar ◽  
Nitin Nitin
Keyword(s):  
Dynamic Programming ◽  
Interconnection Network ◽  
Routing Algorithm ◽  
Networks On Chip ◽  
Mesh Topology ◽  
On Chip

Abstract The performance of the interconnection network doesn’t only depend on the topology, but it also depends on the Routing algorithm used. The simplest Routing algorithm for the mesh topology in networks on chip is the XY Routing algorithm. The level based Routing algorithm has been proved to be more efficient than the XY Routing algorithm. In this paper, level based Routing algorithm using the dynamic programming has been proposed. The proposed Routing algorithm proves to be more efficient in the terms of the computation. The proposed Routing algorithm has achieved up to two times bigger speed.

scholarly journals Central Routing Algorithm: An Alternative Solution to Avoid Mesh Topology in iBGP

2014 ◽  
Vol 37 ◽  
pp. 85-91 ◽  
Author(s):  
Muhammad H. Raza ◽  
Ankit K. Kansara ◽  
Aliraza Nafarieh ◽  
William Robertson
Keyword(s):  
Routing Algorithm ◽  
Alternative Solution ◽  
Mesh Topology

Comparative Performance Analysis of 
Selected Routing Algorithms by Load Variation of 2-Dimensional Mesh Topology Based 
Network-On-Chip

2021 ◽  
Vol 20 (3) ◽  
pp. 1-6
Author(s):  
Mohammed Shaba Saliu ◽  
Muyideen Omuya Momoh ◽  
Pascal Uchenna Chinedu ◽  
Wilson Nwankwo ◽  
Aliu Daniel
Keyword(s):  
Routing Algorithm ◽  
Adaptive Routing ◽  
Injection Rate ◽  
Network On Chip ◽  
Routing Algorithms ◽  
Comparative Performance ◽  
Traffic Pattern ◽  
Mesh Topology ◽  
Similar Vein ◽  
On Chip

Network-on-Chip (NoC) has been proposed as a viable solution to the communication challenges on System-on-Chips (SoCs). As the communication paradigm of SoC, NoCs performance depends mainly on the type of routing algorithm chosen. In this paper different categories of routing algorithms were compared. These include XY routing, OE turn model adaptive routing, DyAD routing and Age-Aware adaptive routing.  By varying the load at different Packet Injection Rate (PIR) under random traffic pattern, comparison was conducted using a 4 × 4 mesh topology. The Noxim simulator, a cycle accurate systemC based simulator was employed. The packets were modeled as a Poisson distribution; first-in-first-out (FIFO) input buffer channel with a depth of five (5) flits and a flit size of 32 bits; and a packet size of 3 flits respectively. The simulation time was 10,000 cycles. The findings showed that the XY routing algorithm performed better when the PIR is low.  In a similar vein, the DyAD routing and Age-aware algorithms performed better when the load i.e. PIR is high.

A Note on the Connectivity of m-Ary n-Dimensional Hypercubes

2019 ◽  
Vol 29 (04) ◽  
pp. 1950017
Author(s):  
Shiying Wang ◽  
Mujiangshan Wang
Keyword(s):  
Fault Tolerance ◽  
Interconnection Networks ◽  
Topology Structure ◽  
Elementary Method

Connectivity plays an important role in measuring the fault tolerance of interconnection networks. As a topology structure of interconnection networks, the m-ary n-dimensional hypercube [Formula: see text] has many good properties. In this paper, we prove, by elementary method, that [Formula: see text] is tightly [Formula: see text] super connected [Formula: see text] and super edge-connected [Formula: see text].

FAULT-TOLERANT COMMUNICATIONS ON HYPERCUBE-CLUSTERS

2000 ◽  
Vol 01 (04) ◽  
pp. 315-329 ◽  
Author(s):  
PETER KOK KEONG LOH ◽  
WEN JING HSU
Keyword(s):  
Fault Tolerance ◽  
Interconnection Networks ◽  
Fault Tolerant ◽  
Routing Algorithm ◽  
Cost Effective ◽  
Hardware Support ◽  
Tolerance Level ◽  
Component Faults ◽  
Message Overhead ◽  
Standard Components

Hierarchical interconnection networks with n-dimensional hypercube clusters can strike a balance between wide application suitability, size scalability as well as reliability. Cluster communications support for such networks must therefore be reliable and efficient without incurring large overheads. This paper proposes a reliable and cost-effective intra-cluster communications strategy for such a class of interconnection networks. The routing algorithm can tolerate up to (n - 1) component faults in the cluster and generates routes that are cycle-free and livelock-free. The message is guaranteed to be optimally (respectively, sub-optimally) delivered within a maximum of n (respectively, 2n - 1) hops. The message overhead incurred is one of the lowest reported for the specified fault tolerance level – with only a single n-bit routing vector accompanying the message to be communicated. Finally, routing hardware support may be simply achieved with standard components, facilitating integration with the host network.

Network-on-Chip Especially for Video Coding Applications Using Multilayer Mesh Topology

2019 ◽  
Vol 12 (3) ◽  
pp. 247-256
Author(s):  
Kamel Messaoudi ◽  
Salah Toumi ◽  
El-Bay Bourennane
Keyword(s):  
Video Coding ◽  
Communication System ◽  
Data Transfer ◽  
Routing Algorithm ◽  
Network On Chip ◽  
Mesh Topology ◽  
Global Interconnects ◽  
And Performance ◽  
On Chip ◽  
Scalable Communication

Background: Network on chip is proposed as new reusable and scalable communication system for applications with important number of IPs. The NoC architecture characteristics are based on several factors: the implementation strategy of IPs, the power dissipation, the placement of IPs, data transfer time, the requirements of the given application, etc. The N×M Mesh topology combined with the XY routing algorithm are generally chosen in many studies. Hardware IPs proposed in the literature, for various applications as example video encoders, operates at different frequencies and generally implemented according to several strategies and different bus sizes. Connecting these IPs using the same communication system is very difficult. Methods: In this paper, we present a new topology based on multi-layer mesh topology and adapted for video coding applications. The proposed topology exploits the video coding information regarding groups of cores that communicate through two cores only. The idea is to use a specific NoC for each group of cores and connect the NoCs with bridge in the positions of two communication cores. The choice of parameters in each NoC depends on the characteristic of IPs in the same group in order to maximize communication adaptivity and performance. Results: Synthesis results show that the proposed multi-layer mesh topology NoC uses much less resources than the traditional NxM mesh topology NoC. Conclusion: This reduction in term of resources is assured by the considerable reduction in the length and number of global interconnects, resulting in an increase in the performance and decrease in the power consumption and area of wire limited circuits.

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