An optimal instruction scheduler for superscalar processor

Hong-Chich Chou;  Chung-Ping Chung

doi:10.1109/71.372778

An optimal instruction scheduler for superscalar processor

IEEE Transactions on Parallel and Distributed Systems ◽

10.1109/71.372778 ◽

1995 ◽

Vol 6 (3) ◽

pp. 303-313 ◽

Cited By ~ 28

Author(s):

Hong-Chich Chou ◽

Chung-Ping Chung

Keyword(s):

Superscalar Processor ◽

Instruction Scheduler

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A backtracking instruction scheduler using predicate-based code hoisting to fill delay slots

Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems - CASES '07 ◽

10.1145/1289881.1289921 ◽

2007 ◽

Cited By ~ 2

Author(s):

Tom Vander Aa ◽

Bing-Feng Mei ◽

Bjorn De Sutter

Keyword(s):

Code Hoisting ◽

Instruction Scheduler

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Building a retargetable local instruction scheduler

Software Practice and Experience ◽

10.1002/(sici)1097-024x(199803)28:3<249::aid-spe152>3.0.co;2-x ◽

1998 ◽

Vol 28 (3) ◽

pp. 249-283 ◽

Cited By ~ 1

Author(s):

Vicki Allan ◽

Steven J. Beaty ◽

Bogong Su ◽

Philip H. Sweany

Keyword(s):

Instruction Scheduler

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Evaluating the Impact of Fault Recovery on Superscalar Processor Performance

2006 12th Pacific Rim International Symposium on Dependable Computing (PRDC'06) ◽

10.1109/prdc.2006.33 ◽

2006 ◽

Cited By ~ 1

Author(s):

Toshinori Sato ◽

Akihiro Chiyonobu

Keyword(s):

Fault Recovery ◽

Superscalar Processor ◽

Processor Performance ◽

The Impact

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Using a resource-limited instruction scheduler to evaluate the iHARP processor

IEE Proceedings - Computers and Digital Techniques ◽

10.1049/ip-cdt:19951622 ◽

1995 ◽

Vol 142 (1) ◽

pp. 23 ◽

Cited By ~ 6

Author(s):

F.L. Steven ◽

G.B. Steven ◽

L. Wang

Keyword(s):

Resource Limited ◽

Instruction Scheduler

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Scheduling on a superscalar processor using the chain technique

Proceedings of the 2014 International Conference on Advanced Mechatronic Systems ◽

10.1109/icamechs.2014.6911578 ◽

2014 ◽

Author(s):

Lin Meng ◽

Nobihiro Moriwaki ◽

Shigeru Oyanagi

Keyword(s):

Superscalar Processor

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Reconfigurable Dynamic Scheduling In Superscalar Processor for FIR Filter

2017 14th IEEE India Council International Conference (INDICON) ◽

10.1109/indicon.2017.8487498 ◽

2017 ◽

Author(s):

S Ramya ◽

B. Rajeshwari

Keyword(s):

Dynamic Scheduling ◽

Fir Filter ◽

Superscalar Processor

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An Instruction Scheduler for Dynamic ALU Cascading Adoption

IPSJ Online Transactions ◽

10.2197/ipsjtrans.2.122 ◽

2009 ◽

Vol 2 ◽

pp. 122-139 ◽

Cited By ~ 4

Author(s):

Jun Yao ◽

Kosuke Ogata ◽

Hajime Shimada ◽

Shinobu Miwa ◽

Hiroshi Nakashima ◽

...

Keyword(s):

Instruction Scheduler

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A framework for statistical modeling of superscalar processor performance

Proceedings Third International Symposium on High-Performance Computer Architecture ◽

10.1109/hpca.1997.569691 ◽

2002 ◽

Cited By ~ 36

Author(s):

D.B. Noonburg ◽

J.P. Shen

Keyword(s):

Statistical Modeling ◽

Superscalar Processor ◽

Processor Performance

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Power Reduction of Superscalar Processor Functional Units by Resizing Adder-Width

Lecture Notes in Computer Science - Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation ◽

10.1007/11556930_5 ◽

2005 ◽

pp. 40-48

Author(s):

Guadalupe Miñana ◽

Oscar Garnica ◽

José Ignacio Hidalgo ◽

Juan Lanchares ◽

José Manuel Colmenar

Keyword(s):

Power Reduction ◽

Superscalar Processor ◽

Functional Units

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A microarchitecture of clustered superscalar processor

2007 7th International Conference on ASIC ◽

10.1109/icasic.2007.4415561 ◽

2007 ◽

Cited By ~ 1

Author(s):

Yang Bing ◽

Mao Zhigang ◽

Gan Chuhui

Keyword(s):

Superscalar Processor

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