Hot-carrier degradation mechanism in narrow- and wide-channel n-MOSFETs with recessed LOCOS isolation structure

2000 ◽  
Vol 21 (3) ◽  
pp. 130-132 ◽  
Author(s):  
Jeffrey Mun Pun Yue ◽  
Wai Kin Chim ◽  
Byung Jin Cho ◽  
Daniel Sin Hung Chan ◽  
Wei Han Qin ◽  
...  
Keyword(s):  
Degradation Mechanism ◽  
Hot Carrier ◽  
Wide Channel ◽  
Hot Carrier Degradation

Hot-carrier degradation mechanism for p-type symmetric LDMOS transistor with thick gate oxide

2012 ◽  
Vol 48 (24) ◽  
pp. 1545-1546 ◽  
Author(s):  
Siyang Liu ◽  
Qinsong Qian ◽  
Weijun Wan ◽  
Tingting Huang ◽  
Weifeng Sun
Keyword(s):  
Degradation Mechanism ◽  
Gate Oxide ◽  
Hot Carrier ◽  
P Type ◽  
Hot Carrier Degradation

A hot-carrier degradation mechanism and electrical characteristics in S/sup 4/D n-MOSFET's

1997 ◽  
Vol 44 (11) ◽  
pp. 2053-2058
Author(s):  
T. Yoshitomi ◽  
M. Saito ◽  
T. Ohguro ◽  
M. Ono ◽  
H.S. Momose ◽  
...  
Keyword(s):  
Degradation Mechanism ◽  
Electrical Characteristics ◽  
Hot Carrier ◽  
Hot Carrier Degradation

Channel Hot Carrier Degradation Mechanism in Long/Short Channel $n$-FinFETs

2013 ◽  
Vol 60 (12) ◽  
pp. 4002-4007 ◽  
Author(s):  
Moonju Cho ◽  
Philippe Roussel ◽  
Ben Kaczer ◽  
Robin Degraeve ◽  
Jacopo Franco ◽  
...  
Keyword(s):  
Degradation Mechanism ◽  
Short Channel ◽  
Hot Carrier ◽  
Hot Carrier Degradation

Device Scaling Effects on Substrate Enhanced Degradation in MOS Transistors

2002 ◽  
Vol 716 ◽  
Author(s):  
Nihar Ranjan Mohapatra ◽  
Souvik Mahapatra ◽  
V. Ramgopal Rao
Keyword(s):  
Flash Memory ◽  
Degradation Mechanism ◽  
Carrier Injection ◽  
Scaling Effects ◽  
Mos Transistors ◽  
Gate Current ◽  
Hot Carrier ◽  
Wide Range ◽  
Injection Mechanism ◽  
Hot Carrier Degradation

AbstractThis paper analyzes in detail the substrate enhanced gate current injection mechanism and the resulting hot-carrier degradation in n-channel MOS transistors and compares the results with conventional channel hot carrier injection mechanism. The degradation mechanism is studied for different values of substrate voltage over a wide range of channel length and oxide thickness. Stress and charge pumping measurements are carried out to study the degradation under identical bias (gate, drain, substrate) and gate current condition. The influence of device dimensions on the gate injection efficiency and hot carrier degradation is also studied. Results show that the degradation under negative substrate voltage operation is strongly dependent on the transverse electric field and spread of the interface trap profile. The possible mechanism responsible for such trends is discussed. It is also found that, under identical gate current (programming time in flash memory cells), the degradation is less for higher negative substrate bias, which is helpful in realizing fast and reliable flash memories.

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