A new model for the post-stress interface trap generation in hot-carrier stressed p-MOSFETs

1999 ◽  
Vol 20 (3) ◽  
pp. 135-137 ◽  
Author(s):  
D.S. Ang ◽  
C.H. Ling
1994 ◽  
Vol 41 (3) ◽  
pp. 413-419 ◽  
Author(s):  
R. Bellens ◽  
E. de Schrijver ◽  
G. Van den Bosch ◽  
G. Groeseneken ◽  
P. Heremans ◽  
...  

1987 ◽  
Vol 34 (6) ◽  
pp. 1359-1365 ◽  
Author(s):  
J. S. Suehle ◽  
T. J. Russell ◽  
K. F. Galloway

1989 ◽  
Author(s):  
F. E. Pagaduan ◽  
A. Hamada ◽  
C. Y. Yang ◽  
E. Takeda

1993 ◽  
Vol 309 ◽  
Author(s):  
Ingrid De Wolf ◽  
Rudi Bellens ◽  
Guido Groeseneken ◽  
Herman E. Maes

AbstractNon-uniform hot-carrier degradation in n-channel polycide-gate MOSFET's with different thicknesses of the poly-Si film, and in p-channel polycide-gate MOSFET's with TiSi2- or CoSi2-gate-silicide, is studied. The n-MOSFET's with the thinnest poly-Si film, show an increased interface trap generation, while the influence of the gate-silicide material on the degradation behaviour of the p-MOSFET's is found to be very small. The results are evaluated in terms of the effect of mechanical stress on the degradation characteristics: favourable for compressive mechanical stress and unfavourable for tensile stress. A correlation with stress measurements by micro-Raman spectroscopy is made.


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