Minimizing floating-body-induced threshold voltage variation in partially depleted SOI CMOS

1996 ◽  
Vol 17 (8) ◽  
pp. 391-394 ◽  
Author(s):  
A. Wei ◽  
D.A. Antoniadis ◽  
L.A. Bair
Keyword(s):  
Threshold Voltage ◽  
Floating Body ◽  
Voltage Variation ◽  
Soi Cmos

A study of the threshold voltage variation for ultra-small bulk and SOI CMOS

2001 ◽  
Vol 48 (9) ◽  
pp. 1995-2001 ◽  
Author(s):  
K. Takeuchi ◽  
R. Koh ◽  
T. Mogami
Keyword(s):  
Threshold Voltage ◽  
Voltage Variation ◽  
Soi Cmos

Efficacy of Ar in reducing the kink effect on floating-body NFD/SOI CMOS

2002 ◽  
Author(s):  
D. Chang ◽  
S. Veeraraghavan ◽  
M. Mendicino ◽  
M. Rashed ◽  
D. Connelly ◽  
...  
Keyword(s):  
Floating Body ◽  
Kink Effect ◽  
Soi Cmos

scholarly journals Ground Plane Impact on Performance of Relaxed Ge FinFETs

2019 ◽  
Vol 14 (1) ◽  
pp. 1-6
Author(s):  
Alberto Vinícius Oliveira ◽  
Guilherme Vieira Gonçalves ◽  
Paula Ghedini Der Agopian ◽  
João Antonio Martino ◽  
Jérôme Mitard ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Computer Aided Design ◽  
Doping Concentration ◽  
Ground Plane ◽  
Subthreshold Swing ◽  
Voltage Variation ◽  
Electrostatic Coupling ◽  
P Type ◽  
Aided Design ◽  
Channel Region

The implementation of a barrier potential layer underneath the channel region, well known as Ground Plane (GP) implantation, and its influence on the performance of relaxed germanium pFinFET devices is investigated in this manuscript. This study aims to explain the fin width dependence of the threshold voltage from experimental data and evaluates the ground plane doping concentration and its depth influence on relaxed p-type channel germanium FinFET parameters, as threshold voltage, transconductance and subthreshold swing, through Technology Computer-Aided Design (TCAD) numerical simulations. The threshold voltage variation reaches up to 80 mV from the narrowest device to the widest one, considering the studied range of ground plane doping concentration. Concerning the subthreshold swing parameter, neither the GP doping concentration, nor its depth play a significant role since the electrostatic coupling is predominant.

Pulse Dependent Threshold Voltage Variation of the Ovonic Threshold Switch in Cross-Point Memory

2020 ◽  
Vol 41 (3) ◽  
pp. 373-376
Author(s):  
Sanghyun Ban ◽  
Hyejung Choi ◽  
Wootae Lee ◽  
Seokman Hong ◽  
Hwanjun Zang ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Cross Point ◽  
Voltage Variation ◽  
Threshold Switch

COMPARATIVE INSTABILITIES ANALYSIS FOR a-Si:H BODY-TIED TFT (BT-TFT) AND FLOATING BODY TFT (FB-TFT) UNDER BIAS TEMPERATURE STRESSING (BTS)

2008 ◽  
Vol 22 (05) ◽  
pp. 337-341
Author(s):  
YONG K. LEE ◽  
SUNG-HOON CHOA
Keyword(s):  
Silicon Nitride ◽  
Threshold Voltage ◽  
Gate Insulator ◽  
Floating Body ◽  
Negative Bias ◽  
Positive Bias ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Bias Stress ◽  
Hole Trapping

The a- Si:H thin film transistors TFT with silicon nitride as a gate insulator have been stressed with negative and positive bias to realize the instability mechanisms. With proposed BT-TFT and FB-TFT devices, it is found that the threshold voltages of both BT-TFT and BT-TFT devices are positively shifted under positive bias stress and then negatively shifted for negative bias stress. The positive threshold voltage shift is due to the electron trapping in the silicon nitride or at the a- Si:H /silicon nitride interface. The negative threshold voltage shift is mainly due to hole trapping and/or electron de-trapping in the silicon nitride or at the a- Si:H /silicon nitride interface. The positive or negative threshold voltage shift keeps increasing with increasing positive or negative gate bias for both BT-TFT and FB-TFT devices. However, as far as the threshold voltage shift slope is concerned, under positive bias stress, both BT-TFT and FB-TFT devices are similar to each other. On the other hand, under negative bias stress, BT-TFT shift amount is much less than one for the FB-TFT device.

A physical model for gate-to-body tunneling current and its effects on floating-body PD/SOI CMOS devices and circuits

2004 ◽  
Vol 48 (2) ◽  
pp. 259-270 ◽  
Author(s):  
Ji-Woon Yang ◽  
Jerry G. Fossum ◽  
Glenn O. Workman ◽  
Cheng-Liang Huang
Keyword(s):  
Physical Model ◽  
Tunneling Current ◽  
Floating Body ◽  
Soi Cmos
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