Resolving the mechanisms of current gain increase under forward current stress in poly emitter n-p-n transistors

1993 ◽  
Vol 14 (5) ◽  
pp. 252-255 ◽  
Author(s):  
J. Zhao ◽  
G.P. Li ◽  
K.Y. Liao ◽  
M.-R. Chin ◽  
J.Y.-C. Sun ◽  
...  
Keyword(s):  
Current Gain ◽  
Current Stress ◽  
Forward Current

High Temperature High Current Gain IC Compatible 4H-SiC Phototransistor

2019 ◽  
Vol 963 ◽  
pp. 832-836 ◽  
Author(s):  
Shuo Ben Hou ◽  
Per Erik Hellström ◽  
Carl Mikael Zetterling ◽  
Mikael Östling
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Room Temperature ◽  
Uv Light ◽  
Optical Power ◽  
Current Gain ◽  
High Current ◽  
Promising Candidate ◽  
Forward Current ◽  
On Chip

This paper presents our in-house fabricated 4H-SiC n-p-n phototransistors. The wafer mapping of the phototransistor on two wafers shows a mean maximum forward current gain (βFmax) of 100 at 25 °C. The phototransistor with the highest βFmax of 113 has been characterized from room temperature to 500 °C. βFmax drops to 51 at 400 °C and remains the same at 500 °C. The photocurrent gain of the phototransistor is 3.9 at 25 °C and increases to 14 at 500 °C under the 365 nm UV light with the optical power of 0.31 mW. The processing of the phototransistor is same to our 4H-SiC-based bipolar integrated circuits, so it is a promising candidate for 4H-SiC opto-electronics on-chip integration.

On the effects of hydrogen in p-n-p transistors under forward current stress in a C-BiCMOS technology

1993 ◽  
Vol 14 (1) ◽  
pp. 4-6 ◽  
Author(s):  
J. Zhao ◽  
G.P. Li ◽  
K.Y. Liao ◽  
M.-R. Chin ◽  
J.Y.-C. Sun
Keyword(s):  
Current Stress ◽  
Forward Current ◽  
Bicmos Technology

Steady-State Analysis of a Normally-Off 4H-SiC Trench Bipolar-Mode FET

2013 ◽  
Vol 740-742 ◽  
pp. 942-945 ◽  
Author(s):  
Fortunato Pezzimenti ◽  
Salvatore Bellone ◽  
Francesco Giuseppe Della Corte ◽  
Roberta Nipoti
Keyword(s):  
Steady State ◽  
Physical Models ◽  
Current Gain ◽  
Low Leakage ◽  
Forward Current ◽  
Low Leakage Current ◽  
Blocking Voltage ◽  
Wide Range ◽  
Bipolar Mode ◽  
A Current

The steady state characteristics of a normally-off 4H-SiC Bipolar Mode FET (BMFET) with a low on-resistance are investigated in a wide range of currents and temperatures by means of an intensive numerical simulation study which clarifies what are the main design constraints. Specific physical models and parameters strictly related to the presently available 4H-SiC technology are carefully taken into account. A drain forward current density up to 500 A/cm2, a specific on-resistance lower than 2 mΩ∙cm2 and a current gain in the order of a few tens are calculated. The blocking voltage is in excess of 1.3 kV with a low leakage current. These results are compared with the experimental data measured in the same test conditions of another SiC power device already introduced to the market.

Comparison of SiC MOSFET Characteristics Following Body-Diode Forward-Current Stress

2019 ◽  
Vol 963 ◽  
pp. 583-587 ◽  
Author(s):  
Ronald Green ◽  
Aivars Lelis ◽  
Franklin Nouketcha
Keyword(s):  
First Generation ◽  
Stacking Faults ◽  
Charge Trapping ◽  
The Body ◽  
Operating Characteristics ◽  
Power Mosfets ◽  
Current Stress ◽  
Forward Current ◽  
Blocking Voltage ◽  
The One

The effect of forward-current stress of the body diode on the operating characteristics of various commercially-available SiC power MOSFETs was compared. The one set of recent-vintage second-generation 1200-V devices studied showed no degradation at all when the body diode was forward conducted—either in the body diode or the MOSFET characteristics. This is a distinct improvement from first generation 1200-V devices from various suppliers. This degradation phenomenon was consistent with the formation of stacking faults during current stress, which typically reduced MOSFET conductivity, and in some devices increased the Off-state leakage current. Although first-generation 1700-V MOSFET characteristics showed no degradation of the body diode, they did experience a degradation of the blocking voltage due to charge trapping during the stress.

Current Gain Stability of SiC Junction Transistors Subjected to Long-Duration DC and Pulsed Current Stress

2016 ◽  
Vol 858 ◽  
pp. 929-932 ◽  
Author(s):  
Siddarth Sundaresan ◽  
Brian Grummel ◽  
Ranbir Singh
Keyword(s):  
Stress Test ◽  
Current Gain ◽  
Pulsed Current ◽  
Similar Extent ◽  
Current Stress ◽  
Current Stressing ◽  
Long Duration ◽  
Current Operation ◽  
Dc Current

The current gain stability of a second generation of 1200 V rated SiC Junction Transistors (SJTs) under long-term DC and pulsed current operation is investigated. A 1000-hour long, 200 A/cm2 DC current stress results in a ≈ 10% reduction of the current gain (β) during the early stages of the stress test, while the β is perfectly stable for the remainder (>90%) of the stress duration. The same amount of stress charge applied as a pulsed current in lieu of DC current results in similar extent of β degradation for the Gen-II SJTs. The pulsed current stressing is conducted at frequencies ranging from 50 kHz to 200 kHz, at a fixed duty cycle of 0.5.

Rapidly Maturing SiC Junction Transistors Featuring Current Gain (β) > 130, Blocking Voltages up to 2700 V and Stable Long-Term Operation

2014 ◽  
Vol 778-780 ◽  
pp. 1001-1004 ◽  
Author(s):  
Siddarth G. Sundaresan ◽  
Stoyan Jeliazkov ◽  
Brian Grummel ◽  
Ranbir Singh
Keyword(s):  
Size Effect ◽  
High Gain ◽  
Current Gain ◽  
High Current ◽  
Current Stress ◽  
Term Operation

SiCnpnJunction Transistors (SJTs) with current gains as high as 132, low on-resistance of 4 mΩ-cm2, and minimal emitter-size effect are demonstrated with blocking voltages > 600 V. 2400 V-class SJTs feature blocking voltages as high as 2700 V combined with on-resistance as low as 5.5 mΩ-cm2. A significant improvement in the current gain stability under long-term high current stress is achieved for the SJTs fabricated by the high gain process.

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