Wafer level forward current reliability analysis of 120GHz production SiGe HBTs under accelerated current stress

2003 ◽  
Author(s):  
J.-S. Rieh ◽  
K. Watson ◽  
F. Guarin ◽  
Z. Yang ◽  
P.-C. Wang ◽  
...  
Keyword(s):  
Reliability Analysis ◽  
Wafer Level ◽  
Current Stress ◽  
Forward Current

Large-size (1.7 × 1.7 mm2) β-Ga2O3 field-plated trench MOS-type Schottky barrier diodes with 1.2 kV breakdown voltage and 109 high on/off current ratio

2021 ◽  
Vol 15 (1) ◽  
pp. 016501
Author(s):  
Fumio Otsuka ◽  
Hironobu Miyamoto ◽  
Akio Takatsuka ◽  
Shinji Kunori ◽  
Kohei Sasaki ◽  
...  
Keyword(s):  
Schottky Barrier ◽  
Leakage Current ◽  
Schottky Barrier Diodes ◽  
Wafer Level ◽  
Current Ratio ◽  
Field Plate ◽  
Low Leakage ◽  
Large Size ◽  
Forward Current ◽  
Low Leakage Current

Abstract We fabricated high forward and low leakage current trench MOS-type Schottky barrier diodes (MOSSBDs) in combination with a field plate on a 12 μm thick epitaxial layer grown by halide vapor phase epitaxy on β-Ga2O3 (001) substrate. The MOSSBDs, measuring 1.7 × 1.7 mm2, exhibited a forward current of 2 A (70 A cm−2) at 2 V forward voltage and a leakage current of 5.7 × 10–10 A at −1.2 kV reverse voltage (on/off current ratio of > 109) with an ideality factor of 1.05 and wafer-level specific on-resistance of 17.1 mΩ · cm2.

Parametric Design and Reliability Analysis of WIT Wafer Level Packaging

2000 ◽  
Author(s):  
Y. T. Lin ◽  
P. J. Tang ◽  
K. N. Chiang
Keyword(s):  
Reliability Analysis ◽  
Flip Chip ◽  
Parametric Design ◽  
Material Selection ◽  
New Technology ◽  
Rapid Expansion ◽  
Wafer Level ◽  
Good Reliability ◽  
Wafer Level Packaging ◽  
Wafer Level Package

Abstract The demands of electronic packages toward lower profile, lighter weight, and higher density of I/O lead to rapid expansion in the field of flip chip, chip scale package (CSP) and wafer level packaging (WLP) technologies. The urgent needs of high I/O density and good reliability characteristic lead to the evolution of the ultra high-density type of non-solder interconnection such as the wire interconnect technology (WIT). The new technology using copper posts to replace the solder bumps as interconnections shown a great improvement in the reliability life. Moreover, this type of wafer level package could achieve higher I/O density, as well as ultra fine pitch. This research will focus on the reliability analysis of the WIT package structures in material selection and structural design, etc. This research will use finite element method to analyze the physical behavior of packaging structures under thermal cycling condition to compare the reliability characteristics of conventional wafer level package and WIT packages. Parametric studies of specific parameters will be performed, and the plastic and temperature dependent material properties will be applied to all of the models.

On the effects of hydrogen in p-n-p transistors under forward current stress in a C-BiCMOS technology

1993 ◽  
Vol 14 (1) ◽  
pp. 4-6 ◽  
Author(s):  
J. Zhao ◽  
G.P. Li ◽  
K.Y. Liao ◽  
M.-R. Chin ◽  
J.Y.-C. Sun
Keyword(s):  
Current Stress ◽  
Forward Current ◽  
Bicmos Technology

Reliability analysis of GaAs/AlGaAs HBTs under forward current/temperature stress

2002 ◽  
Author(s):  
M.E. Hafizi ◽  
L.M. Pawlowicz ◽  
L.T. Tran ◽  
D.K. Umemoto ◽  
D.C. Streit ◽  
...  
Keyword(s):  
Reliability Analysis ◽  
Temperature Stress ◽  
Forward Current
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