The challenge of signal integrity in deep-submicrometer CMOS technology

2001 ◽  
Vol 89 (4) ◽  
pp. 556-573 ◽  
Author(s):  
F. Caignet ◽  
S. Delmas-Bendhia ◽  
E. Sicard
Keyword(s):  
Signal Integrity ◽  
Cmos Technology ◽  
Deep Submicrometer

Color mixing improvement of CMOS image sensor with air-gap-guard ring in deep-submicrometer CMOS technology

2005 ◽  
Vol 26 (5) ◽  
pp. 301-303 ◽  
Author(s):  
T.H. Hsu ◽  
Y.K. Fang ◽  
D.N. Yaung ◽  
S.G. Wuu ◽  
H.C. Chien ◽  
...  
Keyword(s):  
Cmos Image Sensor ◽  
Cmos Technology ◽  
Image Sensor ◽  
Air Gap ◽  
Guard Ring ◽  
Deep Submicrometer ◽  
Color Mixing

A Low-Noise Four-Stage Voltage-Controlled Ring Oscillator in Deep-Submicrometer CMOS Technology

2013 ◽  
Vol 60 (2) ◽  
pp. 71-75 ◽  
Author(s):  
Joo-Myoung Kim ◽  
Seungjin Kim ◽  
In-Young Lee ◽  
Seok-Kyun Han ◽  
Sang-Gug Lee
Keyword(s):  
Cmos Technology ◽  
Low Noise ◽  
Ring Oscillator ◽  
Deep Submicrometer

An Energy Efficient Logic Approach to Implement CMOS Full Adder

2017 ◽  
Vol 26 (05) ◽  
pp. 1750084 ◽  
Author(s):  
Pankaj Kumar ◽  
Rajender Kumar Sharma
Keyword(s):  
Energy Efficient ◽  
High Speed ◽  
Supply Voltage ◽  
Signal Integrity ◽  
Full Adder ◽  
Cmos Technology ◽  
Nand Gate ◽  
Common Environment ◽  
Logic Approach ◽  
Power Delay Product

An energy efficient internal logic approach for designing two 1-bit full adder cells is proposed in this work. It is based on decomposition of the full adder logic into the smaller modules. Low power, high speed and smaller area are the main features of the proposed approach. A modified power aware NAND gate, an essential entity, is also presented. The proposed full adder cells achieve 30.13% and improvement in their power delay product (PDP) metrics when compared with the best reported full adder design. Some of the popular adders and proposed adders are designed with cadence virtuoso tool with UMC 90[Formula: see text]nm technology operating at 1.2[Formula: see text]V supply voltage and UMC 55[Formula: see text]nm CMOS technology operating at 1.0[Formula: see text]V. These designs are tested on a common environment. During the experiment, it is also found that the proposed adder cells exhibit excellent signal integrity and driving capability when operated at low voltages.

STI-Bounded Single-Photon Avalanche Diode in a Deep-Submicrometer CMOS Technology

2006 ◽  
Vol 27 (11) ◽  
pp. 887-889 ◽  
Author(s):  
H. Finkelstein ◽  
M.J. Hsu ◽  
S.C. Esener
Keyword(s):  
Single Photon ◽  
Cmos Technology ◽  
Avalanche Diode ◽  
Deep Submicrometer
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