A total resistance slope-based effective channel mobility extraction method for deep submicrometer CMOS technology

1999 ◽  
Vol 46 (9) ◽  
pp. 1912-1914 ◽  
Author(s):  
G. Niu ◽  
J.D. Cressler ◽  
S.J. Mathew ◽  
S. Subbanna
Keyword(s):  
Extraction Method ◽  
Cmos Technology ◽  
Total Resistance ◽  
Channel Mobility ◽  
Deep Submicrometer ◽  
Effective Channel

The challenge of signal integrity in deep-submicrometer CMOS technology

2001 ◽  
Vol 89 (4) ◽  
pp. 556-573 ◽  
Author(s):  
F. Caignet ◽  
S. Delmas-Bendhia ◽  
E. Sicard
Keyword(s):  
Signal Integrity ◽  
Cmos Technology ◽  
Deep Submicrometer

Electron Scattering in Buried InGaAs MOSFET Channel with HfO2 Gate Oxide

2009 ◽  
Vol 1155 ◽  
Author(s):  
Serge Oktyabrsky ◽  
Padmaja Nagaiah ◽  
Vadim Tokranov ◽  
Sergei Koveshnikov ◽  
Michael Yakimov ◽  
...  
Keyword(s):  
High Mobility ◽  
Gate Oxide ◽  
Cmos Technology ◽  
Interface Layer ◽  
Oxide Interface ◽  
Channel Mobility ◽  
Group Iii ◽  
High K ◽  
Electron Transport Properties ◽  
Group Iii V Semiconductor

AbstractGroup III-V semiconductor materials are being studied as potential replacements for conventional CMOS technology due to their better electron transport properties. However, the excess scattering of carriers in MOSFET channel due to high-k gate oxide interface significantly depreciates the benefits of III-V high-mobility channel materials. We present results on Hall electron mobility of buried QW structures influenced by remote scattering due to InGaAs/HfO2 interface. Mobility in In0.77Ga0.23As QWs degraded from 12000 to 1200 cm2/V-s and the mobility vs. temperature slope changed from T-1.2 to almost T+1.0 in 77-300 K range when the barrier thickness is reduced from 50 to 0 nm. This mobility change is attributed to remote Coulomb scattering due to charges and dipoles at semiconductor/oxide interface. Elimination of the InGaAs/HfO2 interface via introduction of SiOx interface layer formed by oxidation of thin a-Si passivation layer was found to improve the channel mobility. The mobility vs. sheet carrier density shows the maximum close to 2×1012 cm-2.

Electrical Properties of p-Channel MOSFETs Fabricated on 4H- and 6H-SiC

2007 ◽  
Vol 556-557 ◽  
pp. 783-786
Author(s):  
Mitsuo Okamoto ◽  
Mieko Tanaka ◽  
Tsutomu Yatsuo ◽  
Kenji Fukuda
Keyword(s):  
Electrical Properties ◽  
Valence Band ◽  
Threshold Voltage ◽  
Present Report ◽  
Cmos Technology ◽  
Interface State ◽  
Valence Band Edge ◽  
State Distribution ◽  
Channel Mobility ◽  
Temperature Dependences

It is of great importance to investigate the electrical properties of SiC p-channel MOSFETs for development of SiC CMOS technology. In the present report, we investigated dependences of electrical properties of the SiC p-channel MOSFETs on SiC poly-types. The on-state characteristics (channel mobility, threshold voltage, and temperature dependences) for the 4H- and 6H-SiC p-channel MOSFETs showed similar behavior, although those of 4H-SiC n-channel MOSFETs are usually quite different from those of 6H-SiC. These results might be caused by the similar SiC MOS interface state distribution around the valence band edge.

Elevated Temperature Operation of 4H-SiC Nanoribbon Field Effect Transistors

2015 ◽  
Vol 15 (10) ◽  
pp. 7551-7554 ◽  
Author(s):  
Min Seok Kang ◽  
Susanna Yu ◽  
Sang Mo Koo
Keyword(s):  
Elevated Temperature ◽  
Plasma Etching ◽  
Field Effect ◽  
Heat Dissipation ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Top Down ◽  
Channel Mobility ◽  
Channel Thickness ◽  
Effective Channel

We fabricated 4H-SiC nanoribbon field effect transistors (FETs) of various channel thickness (tch) of 100∼500 nm by a “top–down” approach, using a lithography and plasma etching process. We studied the dependence of the device transfer characteristics on the channel geometry. This demonstrated that fabricated SiC nanoribbon FETs with a tch of 100 nm show normally-on characteristics, and have a threshold voltage of −12 V, and a maximum transconductance value of 8.8 mS, which shows improved drain current degradation of the SiC nanoribbon FETs with tch =100 nm at elevated temperature. This can be attributed to the improved heat dissipation, enhanced channel mobility, and together with widening of effective channel thickness depletion induced.

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