scholarly journals Computing the entire active area/power consumption versus delay tradeoff curve for gate sizing with a piecewise linear simulator

1996 ◽  
Vol 15 (11) ◽  
pp. 1424-1434 ◽  
Author(s):  
M.R.C.M. Berkelaar ◽  
P.H.W. Buurman ◽  
J.A.G. Jess
Keyword(s):  
Power Consumption ◽  
Piecewise Linear ◽  
Active Area ◽  
Gate Sizing ◽  
Tradeoff Curve

A Fully Differential Variable Gain Amplifier for Portable Impedance Sensing Applications

2019 ◽  
Vol 7 ◽  
Author(s):  
Jorge Pérez Bailón ◽  
Jaime Ramírez-Angulo ◽  
Belén Calvo ◽  
Nicolás Medrano
Keyword(s):  
Power Consumption ◽  
Active Area ◽  
Variable Gain Amplifier ◽  
Cmos Process ◽  
Current Steering ◽  
Impedance Sensing ◽  
Variable Gain ◽  
Fully Differential ◽  
Sensing Applications ◽  
Constant Bandwidth

This paper presents a Variable Gain Amplifier (VGA) designed in a 0.18 μm CMOS process to operate in an impedance sensing interface. Based on a transconductance-transimpedance (TC-TI) approach with intermediate analog-controlled current steering, it exhibits a gain ranging from 5 dB to 38 dB with a constant bandwidth around 318 kHz, a power consumption of 15.5 μW at a 1.8 V supply and an active area of 0.021 mm2.

scholarly journals 1.0 V-0.18 µm CMOS Tunable Low Pass Filters with 73 dB DR for On-Chip Sensing Acquisition Systems

Electronics ◽  
2021 ◽  
Vol 10 (5) ◽  
pp. 563
Author(s):  
Jorge Pérez-Bailón ◽  
Belén Calvo ◽  
Nicolás Medrano
Keyword(s):  
Power Consumption ◽  
Dynamic Range ◽  
Low Voltage ◽  
Cutoff Frequency ◽  
Cmos Technology ◽  
Active Area ◽  
Current Steering ◽  
Low Pass ◽  
On Chip ◽  
Low Pass Filters

This paper presents a new approach based on the use of a Current Steering (CS) technique for the design of fully integrated Gm–C Low Pass Filters (LPF) with sub-Hz to kHz tunable cut-off frequencies and an enhanced power-area-dynamic range trade-off. The proposed approach has been experimentally validated by two different first-order single-ended LPFs designed in a 0.18 µm CMOS technology powered by a 1.0 V single supply: a folded-OTA based LPF and a mirrored-OTA based LPF. The first one exhibits a constant power consumption of 180 nW at 100 nA bias current with an active area of 0.00135 mm2 and a tunable cutoff frequency that spans over 4 orders of magnitude (~100 mHz–152 Hz @ CL = 50 pF) preserving dynamic figures greater than 78 dB. The second one exhibits a power consumption of 1.75 µW at 500 nA with an active area of 0.0137 mm2 and a tunable cutoff frequency that spans over 5 orders of magnitude (~80 mHz–~1.2 kHz @ CL = 50 pF) preserving a dynamic range greater than 73 dB. Compared with previously reported filters, this proposal is a competitive solution while satisfying the low-voltage low-power on-chip constraints, becoming a preferable choice for general-purpose reconfigurable front-end sensor interfaces.

scholarly journals A CMOS Quadrature Signal Generator for Impedance Spectroscopy Measurement Systems

2018 ◽  
Vol 6 ◽  
Author(s):  
Alejandro Márquez Marzal ◽  
Nicolás Medrano Marqués ◽  
Belén Calvo López ◽  
Pedro A. Martínez Martínez
Keyword(s):  
Impedance Spectroscopy ◽  
Power Consumption ◽  
Signal Generator ◽  
Active Area ◽  
Fully Integrated ◽  
Resolution Power ◽  
Measurement Systems ◽  
Quadrature Signal ◽  
Spectroscopy Measurement ◽  
On Chip

A CMOS fully integrated quadrature signal generator for on-chip impedance spectroscopy (IS) applications is presented. Frequency can be digitally tuned from 5 to 350 kHz with 12-bit resolution. Power consumption is 0.77 mW and active area is 0.129 mm2. Its suitability for the target application is validated with a Randles test impedance cell modelling a protein.

Efficient method to obtain the entire active area against circuit delay time trade-off curve in gate sizing

2005 ◽  
Vol 152 (2) ◽  
pp. 133 ◽  
Author(s):  
J.A. Montiel-Nelson ◽  
J. Sosa ◽  
H. Navarro ◽  
R. Sarmiento ◽  
A. Nunez
Keyword(s):  
Efficient Method ◽  
Delay Time ◽  
Active Area ◽  
Gate Sizing ◽  
Trade Off ◽  
Circuit Delay

scholarly journals Application of NSGA-II to Obtain the Charging Current-Time Tradeoff Curve in Battery Based Underwater Wireless Sensor Nodes

Sensors ◽  
2021 ◽  
Vol 21 (16) ◽  
pp. 5324
Author(s):  
Daniel Rodríguez Rodríguez García ◽  
Juan-A. Montiel-Nelson ◽  
Tomás Bautista ◽  
Javier Sosa
Keyword(s):  
Power Consumption ◽  
Search Strategy ◽  
Sensor Nodes ◽  
Nsga Ii ◽  
Wireless Sensor Nodes ◽  
Current Time ◽  
Time Tradeoff ◽  
Charging Current ◽  
Bisection Search ◽  
Tradeoff Curve

In this paper, a novel application of the Nondominated Sorting Genetic Algorithm II (NSGA II) is presented for obtaining the charging current–time tradeoff curve in battery based underwater wireless sensor nodes. The selection of the optimal charging current and times is a common optimization problem. A high charging current ensures a fast charging time. However, it increases the maximum power consumption and also the cost and complexity of the power supply sources. This research studies the tradeoff curve between charging currents and times in detail. The design exploration methodology is based on a two nested loop search strategy. The external loop determines the optimal design solutions which fulfill the designers’ requirements using parameters like the sensor node measurement period, power consumption, and battery voltages. The inner loop executes a local search within working ranges using an evolutionary multi-objective strategy. The experiments proposed are used to obtain the charging current–time tradeoff curve and to exhibit the accuracy of the optimal design solutions. The exploration methodology presented is compared with a bisection search strategy. From the results, it can be concluded that our approach is at least four times better in terms of computational effort than a bisection search strategy. In terms of power consumption, the presented methodology reduced the required power at least 3.3 dB in worst case scenarios tested.

scholarly journals A Cost-effective Method for Resolution Increase of the Twostage Piecewise Linear ADC Used for Sensor Linearization

2016 ◽  
Vol 16 (1) ◽  
pp. 28-34 ◽  
Author(s):  
Jelena Jovanović ◽  
Dragan Denić
Keyword(s):  
Power Consumption ◽  
Piecewise Linear ◽  
Circuit Complexity ◽  
Cost Effective ◽  
Analog To Digital Converters ◽  
Digital Converter ◽  
Analog To Digital ◽  
Cost Effective Method ◽  
Conversion Stage ◽  
Sensor Linearization

Abstract A cost-effective method for resolution increase of a two-stage piecewise linear analog-to-digital converter used for sensor linearization is proposed in this paper. In both conversion stages flash analog-to-digital converters are employed. Resolution increase by one bit per conversion stage is performed by introducing one additional comparator in front of each of two flash analog-to-digital converters, while the converters’ resolutions remain the same. As a result, the number of employed comparators, as well as the circuit complexity and the power consumption originating from employed comparators are for almost 50 % lower in comparison to the same parameters referring to the linearization circuit of the conventional design and of the same resolution. Since the number of employed comparators is significantly reduced according to the proposed method, special modifications of the linearization circuit are needed in order to properly adjust reference voltages of employed comparators.

scholarly journals Analysis for Joint Delay-Power Tradeoff with Buffer/Channel-Aware and Its FPGA Implementation in Wireless Sensor Networks

Sensors ◽  
2020 ◽  
Vol 20 (11) ◽  
pp. 3114
Author(s):  
Joumana Dakkak ◽  
Saleh Eisa ◽  
Hesham M. El-Badawy ◽  
Ahmed Elbakly
Keyword(s):  
Performance Metrics ◽  
Piecewise Linear ◽  
Arrival Rate ◽  
System Parameters ◽  
System A ◽  
Slow Fading ◽  
Optimal Delay ◽  
Goodness Factor ◽  
Widespread Interest ◽  
Tradeoff Curve

In this paper, we aim to investigate the delay-power tradeoff problem which is attracting widespread interest due to its importance in wireless technology. This research has two main objectives. First, to assess the effect of different system parameters on the performance metrics. Second, to provide a solution for this optimization problem. A two-state, slow-fading channel is categorized into good and bad channel states. An adaptive transmission and random data arrivals are considered in our model. Each channel category has its own Markov chain, which is used in modeling the system. A joint Buffer-Aware and Channel-Aware (BACA) problem was introduced. In addition, an enhanced iterative algorithm was introduced for obtaining a sub-optimal delay-power tradeoff. The results show that the tradeoff curve is piecewise linear, convex and decreasing. Furthermore, a channel-aware system was investigated to provide analysis of the effect of system parameters on the delay and power. The obtained results show that the dominant factors that control the system performance are based on the arrival rate and the channel goodness factor. Moreover, a simplified field programable gate array (FPGA) hardware implementation for the channel aware system scheduler is presented. The implementation results show that the consumed power for the proposed scheduler is 98.5 mW and the maximum processing clock speed is 190 MHz.

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