Efficient method to obtain the entire active area against circuit delay time trade-off curve in gate sizing

2005 ◽  
Vol 152 (2) ◽  
pp. 133 ◽  
Author(s):  
J.A. Montiel-Nelson ◽  
J. Sosa ◽  
H. Navarro ◽  
R. Sarmiento ◽  
A. Nunez
Keyword(s):  
Efficient Method ◽  
Delay Time ◽  
Active Area ◽  
Gate Sizing ◽  
Trade Off ◽  
Circuit Delay

3.3 kV-Class 4H-SiC UMOSFET by Double-Trench with Tilt Angle Ion Implantation

2016 ◽  
Vol 858 ◽  
pp. 974-977 ◽  
Author(s):  
Yusuke Kobayashi ◽  
Shinsuke Harada ◽  
Hiroshi Ishimori ◽  
Shinji Takasu ◽  
Takahito Kojima ◽  
...  
Keyword(s):  
Ion Implantation ◽  
Breakdown Voltage ◽  
Tilt Angle ◽  
Active Area ◽  
Electrical Field ◽  
Trade Off ◽  
Edge Termination ◽  
Trench Structure

A 3.3 kV trench MOSFET with double-trench structure was demonstrated. The deep buried p-base regions were fabricated using tilt angle ion implantation into the sidewalls of the trench contacts. The distance between the trench gate and trench contact was determined through simulation, in order to optimize the trade-off between on-resistance (RonA) and the electrical field in the oxide (Eox). A tapered trench was located in the connective area between the edge termination and the active area, in order to maintain breakdown voltage. We achieved a RonA of 10.3 mWcm2 and a breakdown voltage of 3843 V and the maximum Eox at breakdown voltage was estimated to be 3.2 MV/cm.

Understanding the Trade-Off Between Maximum Passenger Throughput and Airline Equity in Allocating Capacity Under Severe Weather Conditions

2017 ◽  
Vol 2626 (1) ◽  
pp. 18-24 ◽  
Author(s):  
Harika Jayam ◽  
Linda K. Nozick
Keyword(s):  
Optimization Model ◽  
Delay Time ◽  
Weather Conditions ◽  
Severe Weather ◽  
Trade Off ◽  
Ground Delay Program ◽  
Ground Delay ◽  
Time Periods ◽  
Flight Delay

When the capacity at an airport is reduced because of weather conditions, a ground delay program (GDP) is implemented to resolve the discrepancy between demand for arrival slots and the available arrival slots on a given day. GDPs currently ration the available arrival slots via the proportion of arrivals that exist in the schedule by airline (this practice is termed ration by schedule) with an emphasis on equity among the airlines. Existing rationing schemes do not explicitly consider the number of passengers delayed. This study examined the passenger impacts of a focus on seat throughput in reduced capacity conditions for a GDP at a single airport with consideration for airline equity. An optimization model was developed by using the number of seats available in an aircraft as a proxy for number of passengers and an equity term to estimate airline equity implications. A comparison of the current GDP rationing scheme with one focused on seat delay showed that with no change in the total flight delay time periods, passenger throughput could be improved with a threshold placed on equity. The trade-off between airline equity and passenger throughput and the implications of these results are discussed.

scholarly journals Efficient IR Drop Analysis and Alleviation Methodologies Using Dual Threshold Voltages with Gate Resizing Techniques

2015 ◽  
Vol 10 (3) ◽  
pp. 147-157
Author(s):  
Ching-Hwa Cheng
Keyword(s):  
Delay Time ◽  
Timing Analysis ◽  
Estimation Errors ◽  
Ir Drop ◽  
Cell Library ◽  
Circuit Delay ◽  
Threshold Voltages ◽  
Current Consumption ◽  
Gate Resizing ◽  
Drop Impacts

IR drop impacts circuit delay time and reliability. The IR drop comes from unexpected peak current (Ipeak) consumption. This paper proposes an efficient methodology with an in-house EDA tool named IPR to analyze and reduce the Ipeak. IPR adopts dual threshold voltages (Vth) and gate resizing technique; it also lowers the short, dynamic, and static leakage current consumption without degrading the system performance. IPR consists of two parts: Ipeak analysis and Ipeak alleviation processes. Nonlinear static/dynamic timing analysis techniques, in cooperation with dual Vth cell library, provides two kinds of accurate Ipeak calculation methods used in IPR. Using the incremental timing analysis, the Ipeak processing time can be accelerated. Demonstration of the ISCAS89 benchmark circuits shows that IPR can reduce Ipeak by 39%, power consumption by 14%, and delay time by 19%. In addition, it provides 334 times faster computation with 2% and 10% estimation errors of the Ipeak and power in gate-level, respectively, as compared to circuit level simulation results.

Sign in / Sign up

Export Citation Format

Share Document