Combined topological and functionality-based delay estimation using a layout-driven approach for high-level applications

The increasing complexity of VLSI design process has led to an increasing use of layout synthesis systems. For many components of a high-level synthesis system such as module generators and module generator development environments, an accurate model of area and delay for the layouts generated by a layout synthesis system is extremely desirable. We have experimented with a statistical model for area and delay of function modules. This model is surprisingly accurate for a standard cell based layout synthesis systemૼVPNR. The area of adder and shifter modules can be modeled to with in 5% accuracy while the error in delay model is bounded by 4%. This model can be taken through another level of indirection without significant loss in accuracy. The area of all the modules that fit a ripple-template (such as carry-ripple adder) can be modeled with in 30% accuracy. The delay of these modules has a better fit, 15%. The square-template designs (such as array multiplier) have an area model with 1.7% coeificient of variance. In these cases, the model is parametrized by the area and delay of the leaf cells in the template.

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Combined topological and functionality based delay estimation using at layout-driven approach for high level applications

Proceedings EURO-DAC '92: European Design Automation Conference ◽

10.1109/eurdac.1992.246262 ◽

2003 ◽

Cited By ~ 8

Author(s):

C. Ramachandran ◽

F.J. Kurdahi

Keyword(s):

Delay Estimation ◽

High Level

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SCOAP-based Testability Analysis from Hierarchical Netlists

VLSI Design ◽

10.1155/1998/32654 ◽

1998 ◽

Vol 7 (2) ◽

pp. 131-141 ◽

Cited By ~ 1

Author(s):

C. P. Ravikumar ◽

H. Joshi

Keyword(s):

Data Base ◽

Delay Estimation ◽

Efficient Technique ◽

Functional Modules ◽

Analysis Program ◽

Time And Space ◽

Testability Analysis ◽

High Level ◽

Alternative Designs

Circuits of VLSI complexity are designed using modules such as adders, multipliers, register files, memories, multiplexers, and busses. During the high-level design of such a circuit, it is important to be able to consider several alternative designs and compare them on counts of area, performance, and testability. While tools exist for area and delay estimation of module-level circuits, most of the testability analysis tools work on gate-level descriptions of the circuit. Thus an expensive operation of flattening the circuit becomes necessary to carry out testability analysis. In this paper, we describe a time and space-efficient technique for evaluating the well known SCOAP testability measure of a circuit from its hierarchical description with two or more levels of hierarchy. We introduce the notion of SCOAP Expression Diagrams for functional modules, which can be precomputed and stored as part of the module data base. Our hierarchical testability analysis program, HISCOAP, reads the SCOAP expression diagrams for the modules used in the circuit, and evaluates the SCOAP measure in a systematic manner. The program has been implemented on a Sun/SPARC workstation, and we present results on several benchmark circuits, both combinational and sequential. We show that our algorithm also has a straightforward parallel realization.

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