Fast true delay estimation during high level synthesis

1996 ◽  
Vol 15 (9) ◽  
pp. 1088-1105 ◽  
Author(s):  
S. Bhattacharya ◽  
S. Dey ◽  
F. Brglez
Keyword(s):  
High Level Synthesis ◽  
Delay Estimation ◽  
High Level

scholarly journals Statistical Module Level Area and Delay Estimation

VLSI Design ◽  
1997 ◽  
Vol 5 (2) ◽  
pp. 141-153
Author(s):  
Akhilesh Tyagi
Keyword(s):  
Vlsi Design ◽  
Significant Loss ◽  
High Level Synthesis ◽  
Delay Estimation ◽  
Delay Model ◽  
Synthesis System ◽  
Layout Synthesis ◽  
Function Modules ◽  
High Level ◽  
Generator Development

The increasing complexity of VLSI design process has led to an increasing use of layout synthesis systems. For many components of a high-level synthesis system such as module generators and module generator development environments, an accurate model of area and delay for the layouts generated by a layout synthesis system is extremely desirable. We have experimented with a statistical model for area and delay of function modules. This model is surprisingly accurate for a standard cell based layout synthesis systemૼVPNR. The area of adder and shifter modules can be modeled to with in 5% accuracy while the error in delay model is bounded by 4%. This model can be taken through another level of indirection without significant loss in accuracy. The area of all the modules that fit a ripple-template (such as carry-ripple adder) can be modeled with in 30% accuracy. The delay of these modules has a better fit, 15%. The square-template designs (such as array multiplier) have an area model with 1.7% coeificient of variance. In these cases, the model is parametrized by the area and delay of the leaf cells in the template.

Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures

2009 ◽  
Vol E92-A (12) ◽  
pp. 3169-3179 ◽  
Author(s):  
Akira OHCHI ◽  
Nozomu TOGAWA ◽  
Masao YANAGISAWA ◽  
Tatsuo OHTSUKI
Keyword(s):  
High Level Synthesis ◽  
High Level

Exact and Practical Modulo Scheduling for High-Level Synthesis

2019 ◽  
Vol 12 (2) ◽  
pp. 1-26 ◽  
Author(s):  
Julian Oppermann ◽  
Melanie Reuter-Oppermann ◽  
Lukas Sommer ◽  
Andreas Koch ◽  
Oliver Sinnen
Keyword(s):  
High Level Synthesis ◽  
Modulo Scheduling ◽  
High Level
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