Copper Ulsi Interconnect Technology

1998 ◽  
Vol 514 ◽  
Author(s):  
D. Edelstein
Keyword(s):  
High Performance ◽  
Stress Testing ◽  
Cmos Technology ◽  
Functional Verification ◽  
Functional Modules ◽  
Mos Devices ◽  
Potential Problems ◽  
Cu Contamination ◽  
Interconnect Technology ◽  
Better Than

ABSTRACTRecently IBM announced the first implementation of full copper ULSI wiring in a CMOS technology, to be manufactured on its high-performance 0.22 um CMOS products this year. Features of this technology will be presented, as well as functional verification on CMOS chips. To reach this level, extensive yield, reliability, and stress testing had to be done on test and product-like chips, including those packaged into product modules. Data will be presented fom all aspects of this testing, ranging from experiments designed to promote Cu contamination of the MOS devices, to temperature/humidity/bias stressing of assembled functional modules. The results in all areas are shown to be equal to or better than standards set by our current AI(Cu)/Wstud technology. This demonstrates that the potential problems associated with copper wiring that have long been discussed can be overcome.

Advances in imaging SIMS studies of stained and BrdU-labelled human metaphase chromosomes

1995 ◽  
Vol 53 ◽  
pp. 932-933
Author(s):  
R. Levi-Setti ◽  
J. M. Chabala ◽  
R. Espinosa ◽  
M. M. Le Beau
Keyword(s):  
High Performance ◽  
Secondary Ion Mass Spectrometry ◽  
Analytical Sensitivity ◽  
Metaphase Chromosomes ◽  
Banding Patterns ◽  
Sector Mass Spectrometer ◽  
Staining Methods ◽  
The University ◽  
Secondary Ion ◽  
Better Than

We have shown previously that isotope-labelled nucleotides in human metaphase chromosomes can be detected and mapped by imaging secondary ion mass spectrometry (SIMS), using the University of Chicago high resolution scanning ion microprobe (UC SIM). These early studies, conducted with BrdU- and 14C-thymidine-labelled chromosomes via detection of the Br and 28CN- (14C14N-> labelcarrying signals, provided some evidence for the condensation of the label into banding patterns along the chromatids (SIMS bands) reminiscent of the well known Q- and G-bands obtained by conventional staining methods for optical microscopy. The potential of this technique has been greatly enhanced by the recent upgrade of the UC SIM, now coupled to a high performance magnetic sector mass spectrometer in lieu of the previous RF quadrupole mass filter. The high transmission of the new spectrometer improves the SIMS analytical sensitivity of the microprobe better than a hundredfold, overcoming most of the previous imaging limitations resulting from low count statistics.

scholarly journals Performance of Seven Consumer Sleep-Tracking Devices Compared with Polysomnography

SLEEP ◽  
2020 ◽  
Author(s):  
Evan D Chinoy ◽  
Joseph A Cuellar ◽  
Kirbie E Huwa ◽  
Jason T Jameson ◽  
Catherine H Watson ◽  
...  
Keyword(s):  
Performance Measures ◽  
Gold Standard ◽  
High Performance ◽  
Sleep Stage ◽  
Sleep Laboratory ◽  
Sleep Assessment ◽  
Sleep Condition ◽  
Different Populations ◽  
Tracking Devices ◽  
Better Than

Abstract Study Objectives Consumer sleep-tracking devices are widely used and becoming more technologically advanced, creating strong interest from researchers and clinicians for their possible use as alternatives to standard actigraphy. We therefore tested the performance of many of the latest consumer sleep-tracking devices, alongside actigraphy, versus the gold-standard sleep assessment technique, polysomnography (PSG). Methods In total, 34 healthy young adults (22 women; 28.1 ± 3.9 years, mean ± SD) were tested on three consecutive nights (including a disrupted sleep condition) in a sleep laboratory with PSG, along with actigraphy (Philips Respironics Actiwatch 2) and a subset of consumer sleep-tracking devices. Altogether, four wearable (Fatigue Science Readiband, Fitbit Alta HR, Garmin Fenix 5S, Garmin Vivosmart 3) and three non-wearable (EarlySense Live, ResMed S+, SleepScore Max) devices were tested. Sleep/wake summary and epoch-by-epoch agreement measures were compared with PSG. Results Most devices (Fatigue Science Readiband, Fitbit Alta HR, EarlySense Live, ResMed S+, SleepScore Max) performed as well as or better than actigraphy on sleep/wake performance measures, while the Garmin devices performed worse. Overall, epoch-by-epoch sensitivity was high (all ≥0.93), specificity was low-to-medium (0.18-0.54), sleep stage comparisons were mixed, and devices tended to perform worse on nights with poorer/disrupted sleep. Conclusions Consumer sleep-tracking devices exhibited high performance in detecting sleep, and most performed equivalent to (or better than) actigraphy in detecting wake. Device sleep stage assessments were inconsistent. Findings indicate that many newer sleep-tracking devices demonstrate promising performance for tracking sleep and wake. Devices should be tested in different populations and settings to further examine their wider validity and utility.

scholarly journals High Area-Efficient Parallel Encoder with Compatible Architecture for 5G LDPC Codes

Symmetry ◽  
2021 ◽  
Vol 13 (4) ◽  
pp. 700
Author(s):  
Yufei Zhu ◽  
Zuocheng Xing ◽  
Zerun Li ◽  
Yang Zhang ◽  
Yifan Hu
Keyword(s):  
High Performance ◽  
Ldpc Codes ◽  
Low Complexity ◽  
Cmos Technology ◽  
Area Efficiency ◽  
Prior Art ◽  
New Radio ◽  
High Area ◽  
Significant Area ◽  
Area Efficient

This paper presents a novel parallel quasi-cyclic low-density parity-check (QC-LDPC) encoding algorithm with low complexity, which is compatible with the 5th generation (5G) new radio (NR). Basing on the algorithm, we propose a high area-efficient parallel encoder with compatible architecture. The proposed encoder has the advantages of parallel encoding and pipelined operations. Furthermore, it is designed as a configurable encoding structure, which is fully compatible with different base graphs of 5G LDPC. Thus, the encoder architecture has flexible adaptability for various 5G LDPC codes. The proposed encoder was synthesized in a 65 nm CMOS technology. According to the encoder architecture, we implemented nine encoders for distributed lifting sizes of two base graphs. The eperimental results show that the encoder has high performance and significant area-efficiency, which is better than related prior art. This work includes a whole set of encoding algorithm and the compatible encoders, which are fully compatible with different base graphs of 5G LDPC codes. Therefore, it has more flexible adaptability for various 5G application scenarios.

scholarly journals A high-fidelity realization of the Euclid code comparison N-body simulation with Abacus

2019 ◽  
Vol 485 (3) ◽  
pp. 3370-3377 ◽  
Author(s):  
Lehman H Garrison ◽  
Daniel J Eisenstein ◽  
Philip A Pinto
Keyword(s):  
Power Spectrum ◽  
High Performance ◽  
High Fidelity ◽  
Step Size ◽  
Time Step ◽  
Code Comparison ◽  
Force Accuracy ◽  
Integration Errors ◽  
Better Than ◽  
Good Agreement

Abstract We present a high-fidelity realization of the cosmological N-body simulation from the Schneider et al. code comparison project. The simulation was performed with our AbacusN-body code, which offers high-force accuracy, high performance, and minimal particle integration errors. The simulation consists of 20483 particles in a $500\ h^{-1}\, \mathrm{Mpc}$ box for a particle mass of $1.2\times 10^9\ h^{-1}\, \mathrm{M}_\odot$ with $10\ h^{-1}\, \mathrm{kpc}$ spline softening. Abacus executed 1052 global time-steps to z = 0 in 107 h on one dual-Xeon, dual-GPU node, for a mean rate of 23 million particles per second per step. We find Abacus is in good agreement with Ramses and Pkdgrav3 and less so with Gadget3. We validate our choice of time-step by halving the step size and find sub-percent differences in the power spectrum and 2PCF at nearly all measured scales, with ${\lt }0.3{{\ \rm per\ cent}}$ errors at $k\lt 10\ \mathrm{Mpc}^{-1}\, h$. On large scales, Abacus reproduces linear theory better than 0.01 per cent. Simulation snapshots are available at http://nbody.rc.fas.harvard.edu/public/S2016.

Molecular Simulation on Interfacial Structure and Gettering Efficiency of Si (110)/(100) Directly Bonded Hybrid Crystal Orientation Substrates

2009 ◽  
Vol 156-158 ◽  
pp. 199-204
Author(s):  
Hiroaki Kariyazaki ◽  
Tatsuhiko Aoki ◽  
Kouji Izunome ◽  
Koji Sueoka
Keyword(s):  
Molecular Simulation ◽  
Wafer Bonding ◽  
Crystal Orientation ◽  
High Performance ◽  
Cmos Technology ◽  
Experimental Results ◽  
Interfacial Structure ◽  
Atomic Configuration ◽  
Promising Technology ◽  
Bonded Interface

Hybrid crystal orientation technology (HOT) substrates comprised of Si (100) and (110) surface orientation paralleling each <110> direction attract considerable attentions as one of the promising technology for high performance bulk CMOS technology. Although HOT substrates are fabricated by wafer bonding of Si (110) and Si (100) surfaces, it is not clear the atomic configuration of interfacial structure. Furthermore, the possibility for the interface to be an effective gettering source of impurity metals was not well studied. In this paper, we studied the interfacial structure and gettering efficiency of the atomic bonded interface by molecular simulations. The results indicate that the simulated atomic configuration and gettering efficiency of the bonded interface agreed well with the experimental results.

An Offset Reduction Technique for Latch Type Sense Amplifier in High Performance and High Density SRAM

2012 ◽  
Vol 542-543 ◽  
pp. 769-774
Author(s):  
Qun Ling Yu ◽  
Na Bai ◽  
Yan Zhou ◽  
Rui Xing Li ◽  
Jun Ning Chen ◽  
...  
Keyword(s):  
High Performance ◽  
Circuit Simulation ◽  
Cmos Technology ◽  
Optimal Operation ◽  
Reduction Technique ◽  
Total Speed ◽  
Sense Amplifier ◽  
Simulation Results ◽  
A New Technique ◽  
Total Energy Dissipation

A new technique for reducing the offset of latch-type sense amplifier has been proposed and effect of enable signal voltage upon latch-type sense amplifier offset in SRAM has been investigated in this paper. Circuit simulation results on both StrongARM and Double-tail topologies show that the standard deviation of offset can be reduced by 31.23% (StrongARM SA) and 25.2% (Double-tail SA) , respectively, when the voltage of enable signal reaches 0.6V in TSMC 65nm CMOS technology. For a column of bit-cell (1024 bit-cell), the total speed is improved by 14.98% (StrongARAM SA) and 22.26% (Double-tail SA) at the optimal operation point separately, and the total energy dissipation is reduced by 30.45% and 29.47% with this scheme.

A 0.8- mu m CMOS technology for high-performance ASIC memory and channelless gate array

1989 ◽  
Vol 24 (2) ◽  
pp. 380-387 ◽  
Author(s):  
F.-T. Liou ◽  
Y.-P. Han ◽  
F.R. Bryant ◽  
M. Zamanian
Keyword(s):  
High Performance ◽  
Cmos Technology ◽  
Gate Array

A high-performance sub-half micron CMOS technology for fast SRAMs

2003 ◽  
Author(s):  
J. Hayden ◽  
F. Baker ◽  
S. Ernst ◽  
B. Jones ◽  
J. Klein ◽  
...  
Keyword(s):  
High Performance ◽  
Cmos Technology
Sign in / Sign up

Export Citation Format

Share Document