Design of a self-reconfiguring interconnection network for fault-tolerant VLSI processor arrays

1989 ◽  
Vol 38 (1) ◽  
pp. 40-50 ◽  
Author(s):  
S. Pateras ◽  
J. Rajski
Keyword(s):  
Fault Tolerant ◽  
Interconnection Network ◽  
Processor Arrays

DESIGN OF A MULTI-LEVEL FAULT-TOLERANT MESH (MFTM) FOR HIGH RELIABILITY APPLICATIONS

1995 ◽  
Vol 02 (04) ◽  
pp. 419-429
Author(s):  
SHAMBHU J. UPADHYAYA ◽  
I-SHYAN HWANG
Keyword(s):  
System Reliability ◽  
Fault Tolerant ◽  
High Reliability ◽  
Operational Reliability ◽  
Variable Number ◽  
Hierarchical Design ◽  
Processor Arrays ◽  
Design Paradigm ◽  
Multi Level ◽  
Overall Reliability

This paper presents a novel technique for the enhancement of operational reliability of processor arrays by a multi-level fault-tolerant design approach. The key idea of the design is based on the well known hierarchical design paradigm. The proposed fault-tolerant architecture uses a flexible reconfiguration of redundant nodes, thereby offering a better spare utilization than existing two-level redundancy schemes. A variable number of spares is provided at each level of redundancy which enables a flexible reconfiguration as well as area efficient layouts and better spare utilization. The spare nodes at each level can replace any of the failed primary nodes, not only at the same level but also those at the lower levels. The architecture can be adopted to increase the system reliability in Multi Chip Modules (MCMs). The main contributions of our work are the higher degree of fault tolerance, higher overall reliability, flexibility, and a better spare utilization.

scholarly journals Fault-Tolerant Path-Embedding of Twisted Hypercube-Like Networks (THLNs)

Mathematics ◽  
2019 ◽  
Vol 7 (11) ◽  
pp. 1066
Author(s):  
Huifeng Zhang ◽  
Xirong Xu ◽  
Qiang Zhang ◽  
Yuansheng Yang
Keyword(s):  
Topological Structure ◽  
Large Scale ◽  
Fault Tolerant ◽  
Interconnection Network ◽  
Graph Embedding ◽  
Linear Arrays ◽  
Critical Issues ◽  
Vertex Set ◽  
Network Operation ◽  
Host Graph

It is known widely that an interconnection network can be denoted by a graph G = ( V , E ) , where V denotes the vertex set and E denotes the edge set. Investigating structures of G is necessary to design a suitable topological structure of interconnection network. One of the critical issues in evaluating an interconnection network is graph embedding, which concerns whether a host graph contains a guest graph as its subgraph. Linear arrays (i.e., paths) and rings (i.e., cycles) are two ordinary guest graphs (or basic networks) for parallel and distributed computation. In the process of large-scale interconnection network operation, it is inevitable that various errors may occur at nodes and edges. It is significant to find an embedding of a guest graph into a host graph where all faulty nodes and edges have been removed. This is named as fault-tolerant embedding. The twisted hypercube-like networks ( T H L N s ) contain several important hypercube variants. This paper is concerned with the fault-tolerant path-embedding of n-dimensional (n-D) T H L N s . Let G n be an n-D T H L N and F be a subset of V ( G n ) ∪ E ( G n ) with | F | ≤ n - 2 . We show that for two different arbitrary correct vertices u and v, there is a faultless path P u v of every length l with 2 n - 1 - 1 ≤ l ≤ 2 n - f v - 1 - α , where α = 0 if vertices u and v form a normal vertex-pair and α = 1 if vertices u and v form a weak vertex-pair in G n - F ( n ≥ 5 ).

THE CUBE-OF-RINGS INTERCONNECTION NETWORK

1998 ◽  
Vol 09 (01) ◽  
pp. 25-37 ◽  
Author(s):  
THOMAS J. CORTINA ◽  
ZHIWEI XU
Keyword(s):  
Graph Theory ◽  
Interconnection Networks ◽  
Fault Tolerant ◽  
Interconnection Network ◽  
Routing Algorithm ◽  
Parallel Computers ◽  
Closed Form Expression ◽  
Form Expression ◽  
Graph Theoretic ◽  
Basic Graph

We present a family of interconnection networks named the Cube-Of-Rings (COR) networks along with their basic graph-theoretic properties. Aspects of group graph theory are used to show the COR networks are symmetric and optimally fault tolerant. We present a closed-form expression of the diameter and optimal one-to-one routing algorithm for any member of the COR family. We also discuss the suitability of the COR networks as the interconnection network of scalable parallel computers.

Designing a New Class of Fault Tolerant Multistage Interconnection Networks

2005 ◽  
Vol 06 (04) ◽  
pp. 361-382 ◽  
Author(s):  
K. V. Arya ◽  
R. K. Ghosh
Keyword(s):  
Fault Tolerance ◽  
Interconnection Networks ◽  
Fault Tolerant ◽  
Interconnection Network ◽  
Multistage Interconnection Networks ◽  
Multistage Interconnection Network ◽  
New Class

This paper proposes a technique to modify a Multistage Interconnection Network (MIN) to augment it with fault tolerant capabilities. The augmented MIN is referred to as Enhanced MIN (E-MIN). The technique employed for construction of E-MIN is compared with the two known physical fault tolerance techniques, namely, extra staging and chaining. EMINs are found to be more generic than extra staged networks and less expensive than chained networks. The EMIN realizes all the permutations realizable by the original MIN. The routing strategies under faulty and fault free conditions are shown to be very simple in the case of E-MINs.

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