scholarly journals Detailed modeling and reliability analysis of fault-tolerant processor arrays

1992 ◽  
Vol 41 (9) ◽  
pp. 1193-1200 ◽  
Author(s):  
N. Lopez-Benitez ◽  
J.A.B. Fortes
Keyword(s):  
Reliability Analysis ◽  
Fault Tolerant ◽  
Processor Arrays

scholarly journals Reliability analysis of a fault-tolerant RISC-V system-on-chip

2021 ◽  
Vol 125 ◽  
pp. 114346
Author(s):  
Douglas Almeida Santos ◽  
Lucas Matana Luza ◽  
Luigi Dilillo ◽  
Cesar Albenes Zeferino ◽  
Douglas Rossi Melo
Keyword(s):  
Reliability Analysis ◽  
Fault Tolerant ◽  
System On Chip ◽  
On Chip

Loss study and reliability analysis of a new reconfigurable fault‐tolerant multilevel inverter topology

2020 ◽  
Vol 13 (18) ◽  
pp. 4291-4303
Author(s):  
Sai Krishna Saketi ◽  
Pradyumn Chaturvedi ◽  
Dharmendra Yadeo ◽  
Dipesh Atkar
Keyword(s):  
Reliability Analysis ◽  
Fault Tolerant ◽  
Multilevel Inverter ◽  
Inverter Topology

Reliability Analysis of Three Homogeneous Fault-tolerant Inverter Topologies

2016 ◽  
Vol 44 (17) ◽  
pp. 1991-2005 ◽  
Author(s):  
Valeria Boscaino ◽  
Rosario Miceli ◽  
Fabio Genduso ◽  
Frede Blaabjerg
Keyword(s):  
Reliability Analysis ◽  
Fault Tolerant

DESIGN OF A MULTI-LEVEL FAULT-TOLERANT MESH (MFTM) FOR HIGH RELIABILITY APPLICATIONS

1995 ◽  
Vol 02 (04) ◽  
pp. 419-429
Author(s):  
SHAMBHU J. UPADHYAYA ◽  
I-SHYAN HWANG
Keyword(s):  
System Reliability ◽  
Fault Tolerant ◽  
High Reliability ◽  
Operational Reliability ◽  
Variable Number ◽  
Hierarchical Design ◽  
Processor Arrays ◽  
Design Paradigm ◽  
Multi Level ◽  
Overall Reliability

This paper presents a novel technique for the enhancement of operational reliability of processor arrays by a multi-level fault-tolerant design approach. The key idea of the design is based on the well known hierarchical design paradigm. The proposed fault-tolerant architecture uses a flexible reconfiguration of redundant nodes, thereby offering a better spare utilization than existing two-level redundancy schemes. A variable number of spares is provided at each level of redundancy which enables a flexible reconfiguration as well as area efficient layouts and better spare utilization. The spare nodes at each level can replace any of the failed primary nodes, not only at the same level but also those at the lower levels. The architecture can be adopted to increase the system reliability in Multi Chip Modules (MCMs). The main contributions of our work are the higher degree of fault tolerance, higher overall reliability, flexibility, and a better spare utilization.

Sign in / Sign up

Export Citation Format

Share Document