Limit of gate oxide thickness scaling in MOSFETs due to apparent threshold voltage fluctuation induced by tunnel leakage current

2001 ◽  
Vol 48 (2) ◽  
pp. 259-264 ◽  
Author(s):  
M. Koh ◽  
W. Mizubayashi ◽  
K. Iwamoto ◽  
H. Murakami ◽  
T. Ono ◽  
...  
Keyword(s):  
Leakage Current ◽  
Threshold Voltage ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Voltage Fluctuation ◽  
Gate Oxide Thickness

Demonstration of Asymmetric Gate-Oxide Thickness Four-Terminal FinFETs Having Flexible Threshold Voltage and Good Subthreshold Slope

2007 ◽  
Vol 28 (3) ◽  
pp. 217-219 ◽  
Author(s):  
Meishoku Masahara ◽  
Radu Surdeanu ◽  
Liesbeth Witters ◽  
Gerben Doornbos ◽  
Viet H. Nguyen ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Subthreshold Slope ◽  
Gate Oxide Thickness

scholarly journals Atomic-scale ferroic HfO2-ZrO2 superlattice gate stack for advanced transistors

2021 ◽  
Author(s):  
Suraj Cheema ◽  
Nirmaan Shanker ◽  
Li-Chen Wang ◽  
Cheng-Hsiang Hsu ◽  
Shang-Lin Hsu ◽  
...  
Keyword(s):  
Leakage Current ◽  
High Performance ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Atomic Scale ◽  
Oxide Semiconductor ◽  
Operating Voltage ◽  
Gate Stacks ◽  
Gate Stack ◽  
Gate Oxide Thickness

Abstract With the scaling of lateral dimensions in advanced transistors, an increased gate capacitance is desirable both to retain the control of the gate electrode over the channel and to reduce the operating voltage. This led to the adoption of high-κ dielectric HfO2 in the gate stack in 2008, which remains as the material of choice to date. Here, we report HfO2-ZrO2 superlattice heterostructures as a gate stack, stabilized with mixed ferroelectric-antiferroelectric order, directly integrated onto Si transistors and scaled down to ~ 20 Å, the same gate oxide thickness required for high performance transistors. The overall EOT (equivalent oxide thickness) in metal-oxide-semiconductor capacitors is equivalent to ~ 6.5 Å effective SiO2 thickness, which is, counterintuitively, even smaller than the interfacial SiO2 thickness (8.0-8.5 Å) itself. Such a low effective oxide thickness and the resulting large capacitance cannot be achieved in conventional HfO2-based high-κ dielectric gate stacks without scavenging the interfacial SiO2, which has adverse effects on the electron transport and gate leakage current. Accordingly, our gate stacks, which do not require such scavenging, provide substantially lower leakage current and no mobility degradation. Therefore, our work demonstrates that HfO2-ZrO2 multilayers with competing ferroelectric-antiferroelectric order, stabilized in the 2 nm thickness regime, provides a new path towards advanced gate oxide stacks in electronic devices beyond the conventional HfO2-based high-κ dielectrics.

A Model of Threshold Voltage in FinFET

2011 ◽  
Vol 216 ◽  
pp. 167-170
Author(s):  
Jian Liu ◽  
Li Li ◽  
X.H. Zhang
Keyword(s):  
Numerical Simulation ◽  
Threshold Voltage ◽  
Doping Concentration ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Polysilicon Gate ◽  
Gate Oxide Thickness ◽  
Threshold Voltage Model

A physics-based threshold voltage model is proposed, according to the electrostatics distribution in Si body of FinFET which is obtained by 2-D numerical simulation. Threshold voltage of FinFET calculated from the model is matched with results of numerical simulation. Influences of polysilicon gate doping concentration, Si body doping concentration, the width and height of Si body and the gate oxide thickness on threshold voltage were investigated. As results,Si body doping concentration, gate doping concentration and the width of Si body have been found to be the most important parameters for the design of threshold voltage of FinFET-like devices.

Performance Improvement of >10kV SiC IGBTs with Retrograde p-Well

2019 ◽  
Vol 963 ◽  
pp. 639-642 ◽  
Author(s):  
Amit K. Tiwari ◽  
Marina Antoniou ◽  
Neo Lophitis ◽  
Samuel Perkins ◽  
Tatjana Trajkovic ◽  
...  
Keyword(s):  
Performance Improvement ◽  
High Voltage ◽  
Threshold Voltage ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Low Energy ◽  
Doping Profile ◽  
Doping Density ◽  
Gate Oxide Thickness ◽  
Promising Solution

A p-well consisting of a retrograde doping profile is investigated for performance improvement of >10kV SiC IGBTs. The retrograde p-well, which can be realized using low-energy shallow implants, effectively addresses the punch-through, a common issue in high-voltage vertical architectures consisting of a conventional p-well with typical doping density of 1e17cm-3 and depth 1μm. The innovative approach offers an extended control over the threshold voltage. Without any punch-through, a threshold voltage in the range 6V-7V is achieved with gate-oxide thickness of 100nm. Gate oxide thickness is typically restricted to 50nm if a conventional p-well with doping density of 1e17cm-3 is utilized. We therefore propose a highly promising solution, the retrograde p-well, for the development of >10kV SiC IGBTs.

Improved Device Performance of In0.5Ga0.5P/In0.22Ga0.78As/GaAs MOS p-HEMT using a Selective Liquid Phase Oxidation

2002 ◽  
Vol 744 ◽  
Author(s):  
I-H Kang ◽  
J-W Lee ◽  
S-J Kang ◽  
S-J Jo ◽  
S-K In ◽  
...  
Keyword(s):  
Liquid Phase ◽  
Oxide Layer ◽  
Threshold Voltage ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Liquid Phase Oxidation ◽  
Device Performance ◽  
Gate Oxide Thickness ◽  
Phase Oxidation ◽  
Rf Performances

ABSTRACTThe DC and RF characteristics of In0.5Ga0.5P/In0.22Ga0.78As/GaAs MOS p-HEMTs with different gate oxide thickness were investigated and compared with those of Schottky-gate p-HEMT without the gate oxide layer. The oxide layer was implemented by using a liquid phase oxidation technique. It was found that transconductance (gm), threshold voltage and breakdown voltage characteristics of MOS p-HEMTs depended strongly on the gate oxide thickness. The MOS p-HEMTs showed superior DC and RF performances compared with those of GaAs-based MOSFET having oxide/n-GaAs or oxide/InGaAs interface.

LEAKAGE CURRENT IN DEEP-SUBMICRON CMOS CIRCUITS

2002 ◽  
Vol 11 (06) ◽  
pp. 575-600 ◽  
Author(s):  
KAUSHIK ROY ◽  
SAIBAL MUKHOPADHYAY ◽  
HAMID MAHMOODI-MEIMAND
Keyword(s):  
Leakage Current ◽  
Power Dissipation ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Channel Length ◽  
Deep Submicron ◽  
Cmos Circuits ◽  
Weak Inversion ◽  
Gate Oxide Thickness ◽  
Gate Oxide Tunneling

The high leakage current in deep submicron regimes is becoming a significant contributor to the power dissipation of CMOS circuits as the threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for the estimation and reduction of leakage power, especially in the low power applications. This paper explores the various transistor intrinsic leakage mechanisms including the weak inversion, the drain-induced barrier lowering, the gate-induced drain leakage, and the gate oxide tunneling.

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