Vertical bipolar transistors fabricated in local silicon on insulator films prepared using confined lateral selective epitaxial growth (CLSEG)

1990 ◽  
Vol 37 (11) ◽  
pp. 2336-2342 ◽  
Author(s):  
P.J. Schubert ◽  
G.W. Neudeck
Keyword(s):  
Epitaxial Growth ◽  
Bipolar Transistors ◽  
Silicon On Insulator ◽  
Selective Epitaxial Growth

A complementary selective epitaxial growth (CSEG) process and its application to high speed bipolar transistors

2002 ◽  
Author(s):  
J.W. Osenbach ◽  
A. Feygenson ◽  
H.C. Praefcke ◽  
A.J. Laduca ◽  
J.P. Gardner ◽  
...  
Keyword(s):  
Epitaxial Growth ◽  
High Speed ◽  
Bipolar Transistors ◽  
Selective Epitaxial Growth

Multiple layers of silicon-on-insulator islands fabrication by selective epitaxial growth

1999 ◽  
Vol 20 (5) ◽  
pp. 194-196 ◽  
Author(s):  
Sangwoo Pae ◽  
Taichi Su ◽  
J.P. Denton ◽  
G.W. Neudeck
Keyword(s):  
Epitaxial Growth ◽  
Silicon On Insulator ◽  
Selective Epitaxial Growth

Electron microscopy of defects in silicon-on-insulator structures formed by selective epitaxial growth

1993 ◽  
Vol 51 ◽  
pp. 798-799
Author(s):  
Z. S. H. Weng-Sieh ◽  
J. C. Lou ◽  
W. G. Oldham ◽  
R. Gronsky
Keyword(s):  
Epitaxial Growth ◽  
Integrated Circuit ◽  
Silicon Substrate ◽  
New Technology ◽  
Three Dimensional ◽  
Chemical Vapor ◽  
Nucleation And Growth ◽  
Silicon On Insulator ◽  
Epitaxial Silicon ◽  
Selective Epitaxial Growth

In the interest of obtaining increased integrated circuit device density, a relatively new technology known as selective epitaxial growth (SEG) of silicon is being explored, especially for improved isolation of devices including possible three dimensional (vertical) integration. This technology involves the deposition and selective nucleation and growth of silicon from the vapor phase, seeded by the silicon substrate. The process is “selective” because nucleation and growth occurs on the silicon substrate but is prohibited on the oxide. The epitaxial silicon proceeds to grow upward and laterally over the oxide.Silicon deposition was performed in a horizontal hot-walled low pressure chemical vapor deposition (LPCVD) reactor. A dry thermal oxide was grown on the substrates, patterned, and etched to create seed windows. A 900 °C prebake was performed at a pressure of 6 torr in a hydrogen ambient for a period of 15 minutes, with in some cases, a small concentration (approximately 0.025%) of dichlorosilane (DCS) gas, and deposition was performed at 850 °C through the decomposition of DCS gas: SiH2Cl2 -> Si(s)+ 2HCl(g).

Reduction of Base Access Resistance in AlGaN/GaN Heterojunction Bipolar Transistors using GaInN Base Cap Layer and Selective Epitaxial Growth

2005 ◽  
Vol 892 ◽  
Author(s):  
Jay M Shah ◽  
Thomas Gessmann ◽  
Hong Luo ◽  
Yangang Xi ◽  
Kaixuan Chen ◽  
...  
Keyword(s):  
Contact Resistance ◽  
Epitaxial Growth ◽  
Heterojunction Bipolar Transistors ◽  
Bipolar Transistors ◽  
Current Gain ◽  
Selective Epitaxial Growth ◽  
Offset Voltage ◽  
Specific Contact ◽  
Access Resistance ◽  
P Type

AbstractOne of the major challenges affecting the performance of Npn AlGaN/GaN heterojunction bipolar transistors (HBTs) is the high base access resistance, which is comprised of the base contact resistance and the base bulk resistance. A novel concept is proposed to reduce the base access resistance in Npn AlGaN/GaN HBTs by employing polarization-enhanced contacts and selective epitaxial growth of the base and emitter. In addition, this technique reduces the exposed base surface area, which results in a lower surface recombination current. Such a structure would enable better performance of AlGaN/GaN HBTs in terms of higher current gain and a lower offset voltage. Theoretical calculations on polarization-enhanced contacts predict p-type specific contact resistance lower than 10-5 Ωcm2. Experimental results using transmission line measurement (TLM) technique yield specific contact resistances of 5.6×10-4 Ωcm2 for polarization-enhanced p-type contacts and 7.8×10-2 Ωcm2 for conventional p-type contacts.

Selective epitaxial growth in silicon on insulator: Planarity and mass flow

1989 ◽  
Vol 65 (9) ◽  
pp. 3718-3721 ◽  
Author(s):  
D. A. Williams ◽  
R. A. McMahon ◽  
H. Ahmed ◽  
G. Garry ◽  
L. Karapiperis ◽  
...  
Keyword(s):  
Epitaxial Growth ◽  
Mass Flow ◽  
Silicon On Insulator ◽  
Selective Epitaxial Growth

Improvements in Zone Melt Recrystallized Soi Layers by the Use of Selective Epitaxial Growth in the Seed Windows.

1987 ◽  
Vol 107 ◽  
Author(s):  
D.A. Williams ◽  
R.A. McMahon ◽  
H. Ahmed ◽  
L. Karapiperis ◽  
G. Garry ◽  
...  
Keyword(s):  
Epitaxial Growth ◽  
Three Dimensional ◽  
Silicon Layer ◽  
Silicon On Insulator ◽  
Cross Sectional ◽  
Selective Epitaxial Growth ◽  
Beam System ◽  
Transmission Electron ◽  
The One ◽  
Zone Melt

AbstractThe effect of selective epitaxial growth (SEG) of silicon in the seed windows of silicon on insulator structures prior to recrystallization has been investigated. Subsequent zone melt recrystallization of these structures was performed in a dual electron beam system, and it was found that the full planarisation of the deposited silicon layer results in uniform film thickness after recrystallization. Cross sectional scanning and transmission electron microscopy, optical microscopy after defect etching, and bevelling are used to analyse the material. The SEG method improves the uniformity of the film for device island etching, and so is useful for all silicon on insulator applications, although the one of most interest for these investigations is the production of three dimensional circuitry. This is achieved by stacking layers of devices, and so planarity is particularly important.

Sign in / Sign up

Export Citation Format

Share Document