Characterization of nonlinear substrate resistance in short-channel MOSFETs

1996 ◽  
Vol 43 (12) ◽  
pp. 2177-2184
Author(s):  
A. Mihnea ◽  
S.S. Georgescu
Author(s):  
Yuk L. Tsang ◽  
Xiang D. Wang ◽  
Reyhan Ricklefs ◽  
Jason Goertz

Abstract In this paper, we report a transistor model that has successfully led to the identification of a non visual defect. This model was based on detailed electrical characterization of a MOS NFET exhibiting a threshold voltage (Vt) of just about 40mv lower than normal. This small Vt delta was based on standard graphical extrapolation method in the usual linear Id-Vg plots. We observed, using a semilog plot, two slopes in the Id-Vg curves with Vt delta magnified significantly in the subthreshold region. The two slopes were attributed to two transistors in parallel with different Vts. We further found that one of the parallel transistors had short channel effect due to a punch-through mechanism. It was proposed and ultimately confirmed the cause was due to a dopant defect using scanning capacitance microscopy (SCM) technique.


Author(s):  
Abhishek A. Sharma ◽  
Rohan Shelar ◽  
Rishkul Kulkarni ◽  
Apeksha Shenoy ◽  
Pranit Kalantri ◽  
...  
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1991 ◽  
Vol 74 (5) ◽  
pp. 379-387
Author(s):  
R. Mahnkopf ◽  
G. Przyrembel ◽  
H. G. Wagemann

VLSI Design ◽  
2008 ◽  
Vol 2008 ◽  
pp. 1-5
Author(s):  
Sotoudeh Hamedi-Hagh ◽  
Ahmet Bindal

Vertical nanowire surrounding gate field effect transistors (SGFETs) provide full gate control over the channel to eliminate short-channel effects. This paper presents design and characterization of a differential pair amplifier using NMOS and PMOS SGFETs with a 10 nm channel length and a 2 nm channel radius. The amplifier dissipates 5 μW power and provides 5 THz bandwidth with a voltage gain of 16, a linear output voltage swing of 0.5 V, and a distortion better than 3% from a 1.8 V power supply and a 20 aF capacitive load. The 2nd- and 3rd-order harmonic distortions of the amplifier are −40 dBm and −52 dBm, respectively, and the 3rd-order intermodulation is −24 dBm for a two-tone input signal with 10 mV amplitude and 10 GHz frequency spacing. All these parameters indicate that vertical nanowire surrounding gate transistors are promising candidates for the next generation high-speed analog and VLSI technologies.


1991 ◽  
Vol 75 (1) ◽  
pp. 8-8
Author(s):  
Beitrag R. Mahnkopf ◽  
G. Przyrembel ◽  
H. G. Wagemann

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