Formation of cobalt silicided shallow junction using implant into/through silicide technology and low temperature furnace annealing

1996 ◽  
Vol 43 (2) ◽  
pp. 258-266 ◽  
Author(s):  
Bin-Shing Chen ◽  
Mao-Chieh Chen
Keyword(s):  
Low Temperature ◽  
Furnace Annealing ◽  
Shallow Junction ◽  
Temperature Furnace

Silicon Bipolar Transistors Fabricated using Ion Implantation and Laser Annealing

1980 ◽  
Vol 1 ◽  
Author(s):  
Nobuyoshi Natsuaki ◽  
Takao Miyazaki ◽  
Makoto Ohkura ◽  
Toru Nakamura ◽  
Masao Tamura ◽  
...  
Keyword(s):  
Low Temperature ◽  
Laser Pulse ◽  
Laser Irradiation ◽  
Ruby Laser ◽  
Laser Annealing ◽  
Bipolar Transistors ◽  
Pulse Irradiation ◽  
Irradiation Effects ◽  
Furnace Annealing ◽  
Temperature Furnace

ABSTRACTBipolar transistors with laser annealed base and emitter, as well as those with furnace annealed base and laser annealed emitter, have been successfully fabricated using Q-switched ruby laser pulse irradiation. The performance of laser asannealed transistors is rather poor. However, it can be improved, to some extent, by relatively low temperature furnace annealing after laser irradiation. DC and RF characteristics of laser annealed transistors are presented in conjunction with laser irradiation effects on the characteristics of conventionally fabricated transistors.

Cobalt Contamination in Silicon

2005 ◽  
Vol 108-109 ◽  
pp. 571-576 ◽  
Author(s):  
Maria Luisa Polignano ◽  
Daniele Caputo ◽  
Davide Codegoni ◽  
Vittorio Privitera ◽  
M. Riva
Keyword(s):  
Low Temperature ◽  
Cobalt Concentration ◽  
High Concentration ◽  
Furnace Annealing ◽  
Type Silicon ◽  
P Type ◽  
Temperature Furnace

The properties of cobalt as a contaminant in p-type silicon are studied by using cobaltimplanted wafers annealed by RTP or by RTP plus a low temperature furnace annealing. It is shown that after RTP most cobalt is under the form of CoB pairs. A quantification of cobalt contamination is provided based upon SPV measurements and optical pair dissociation. However, this quantification fails in furnace-annealed wafers because of the formation of a different level. It is shown that the CoB level is located near the band edges, whereas the level formed upon a low temperature furnace annealing is located near midgap. Besides, when the cobalt concentration is high enough a small fraction of cobalt is in a level different from the CoB pair even in RTP samples. This level can probably be identified with a previously observed midgap level. It is suggested that the same level is formed in RTP plus low temperature furnace annealed samples and in high concentration RTP annealed samples, and that this level may consist in some cobalt agglomerate.

Formation of NiSi-Silicided p + n Shallow Junctions Using Implant Through Silicide and Low Temperature Furnace Annealing

2003 ◽  
Vol 765 ◽  
Author(s):  
Chao-Chun Wang ◽  
Chiao-Ju Lin ◽  
Mao-Chieh Chen
Keyword(s):  
Activation Energy ◽  
Low Temperature ◽  
Thermal Annealing ◽  
Reverse Bias ◽  
Reverse Current ◽  
Furnace Annealing ◽  
Silicide Layer ◽  
Shallow Junctions ◽  
Higher Temperature ◽  
Temperature Furnace

AbstractNiSi-silicided p+n shallow junctions are fabricated using BF2+ implantation into/through thin NiSi silicide layer (ITS technology) followed by low temperature furnace annealing (from 550 to 800°C). The NiSi film agglomerates following a thermal annealing at 600°C, and may result in the formation of discontinuous islands at a higher temperature. The incorporation of fluorine atoms in the NiSi film can retard the formation of film agglomeration and thus improve the film's thermal stability. A forward ideality factor of about 1.02 and a reverse current density of about 1nA/cm2 can be attained for the NiSi(310Å)/p+n junctions fabricated by BF2+ implantation at 35 keV to a dose of 5×1015cm-2 followed by a 650°C thermal annealing; the junction formed is about 60nm measured from the NiSi/Si interface. Activation energy measurements show that the reverse bias junction currents are dominated by the diffusion current, indicating that most of the implanted damages can be recovered after annealing at a temperature as low as 650°C.

Effects of Laser Annealing on the Furnace Annealed Amorphous Silicon Thin Films

1996 ◽  
Vol 420 ◽  
Author(s):  
Kwon-Young Choi ◽  
Jae-Hong Jeon ◽  
Min-Koo Han ◽  
Yong-Sang Kim
Keyword(s):  
Thin Film ◽  
Low Temperature ◽  
Excimer Laser ◽  
Thin Film Transistors ◽  
Laser Annealing ◽  
Excimer Laser Annealing ◽  
Furnace Annealing ◽  
Average Grain Size ◽  
Polysilicon Films ◽  
Temperature Furnace

AbstractThe performance of polysilicon thin film transistors fabricated by two-step annealing, which consists of furnace annealing and subsequent excimer laser annealing, is described. It was found that the average grain size of low temperature furnace annealed polysilicon films was several times larger than that of excimer laser annealed polysilicon films while the density of in-grain defect in low temperature furnace annealed films was much higher than that of excimer laser annealed film. The device characteristics of the low temperature furnace annealed polysilicon thin film transistors were improved significantly by postannealing, such as high temperature furnace annealing and excimer laser annealing, due to the effective elimination of in-grain defects. The density of trap states, which was extracted from the transfer curves of polysilicon thin film transistors, was used to demonstrate the effects of modifying the deep and tail trap levels by two-step annealing.

Characteristics of Short-Channel Mosfet's in Laser Crystallized Si-on-Insulator

1983 ◽  
Vol 23 ◽  
Author(s):  
K. K. Ng ◽  
G. K. Celler ◽  
E. I. Povilonis ◽  
L. E. Trimble ◽  
S. M. Sze
Keyword(s):  
Low Temperature ◽  
Grain Boundaries ◽  
Bulk Material ◽  
Silicon On Insulator ◽  
Ring Oscillators ◽  
Short Channel ◽  
Furnace Annealing ◽  
Enhanced Diffusion ◽  
Channel Lengths ◽  
Temperature Furnace

ABSTRACTData are reported on short-channel MOSFET's fabricated in laser crystallized silicon-on-insulator (SOI) structures. In this experiment, special effort was made to minimize enhanced diffusion of dopants from the source and drain regions along grain boundaries. Instead of the standard anneal used for the implant activation, rapid thermal annealing and low temperature furnace annealing were used. These modified processes yielded functional MOSFET's with channel lengths as short as 1.5 μm, and ring oscillators of 2.0 μm. A speed of 115 ps per stage was obtained in these ring oscillators which is not only the fastest ever reported on any SOI structure, but also a factor of 2 faster than that from the same circuits in bulk Si. The results demonstrate quantitatively the speed improvement of SOI over bulk material due to reduced parasitic capacitance.

Formation of PtSi‐contactedp+nshallow junctions by BF+2implantation and low‐temperature furnace annealing

1991 ◽  
Vol 69 (8) ◽  
pp. 4354-4363 ◽  
Author(s):  
Bing‐Yue Tsui ◽  
Jiunn‐Yann Tsai ◽  
Mao‐Chieh Chen
Keyword(s):  
Low Temperature ◽  
Furnace Annealing ◽  
Temperature Furnace
Sign in / Sign up

Export Citation Format

Share Document