Hetero-emitter-like characteristics of phosphorus doped polysilicon emitter transistors. Part II: band deformation due to residual stress in the polysilicon emitter

1995 ◽  
Vol 42 (3) ◽  
pp. 427-435 ◽  
Author(s):  
M. Kondo ◽  
T. Kobayashi ◽  
Y. Tamaki
Keyword(s):  
Residual Stress ◽  
Band Deformation ◽  
Polysilicon Emitter ◽  
Phosphorus Doped

A 64-GHz f/sub T/ and 3.6-V BV/sub CEO/ Si bipolar transistor using in situ phosphorus-doped and large-grained polysilicon emitter contacts

1993 ◽  
Vol 40 (8) ◽  
pp. 1563-1565 ◽  
Author(s):  
M. Nanba ◽  
T. Uchino ◽  
M. Kondo ◽  
T. Nakamura ◽  
T. Kobayashi ◽  
...  
Keyword(s):  
Bipolar Transistor ◽  
Polysilicon Emitter ◽  
Phosphorus Doped

Effect of annealing on polysilicon emitter transistors

1989 ◽  
Vol 67 (4) ◽  
pp. 179-183 ◽  
Author(s):  
E. P. Keyes ◽  
N. G. Tarr
Keyword(s):  
Furnace Annealing ◽  
Polysilicon Emitters ◽  
Polysilicon Emitter ◽  
Phosphorus Doped ◽  
Tolerable Level

The effect of 900 °C furnace annealing on transistors with in situ phosphorus-doped polysilicon emitters has been investigated. For devices with chemically grown interfacial oxides, annealing is essential to give acceptable emitter resistance and emitter Gummel numbers. For devices lacking an intentionally grown interfacial oxide, annealing is necessary to reduce the emitter resistance to a tolerable level, but it simultaneously lowers the emitter Gummel number.

Effect of rapid epitaxy in in situ phosphorus-doped polysilicon emitter on current-gain of bipolar transistors

1996 ◽  
Vol 43 (8) ◽  
pp. 1281-1285 ◽  
Author(s):  
T. Shiba ◽  
M. Kondo ◽  
T. Uchino ◽  
H. Murakoshi ◽  
Y. Tamaki
Keyword(s):  
Bipolar Transistors ◽  
Current Gain ◽  
Polysilicon Emitter ◽  
Phosphorus Doped

Rapid thermal annealing of in situ phosphorus-doped polysilicon emitters

1992 ◽  
Vol 70 (10-11) ◽  
pp. 1109-1111 ◽  
Author(s):  
Gary F. Mackay ◽  
Brendon M. Manning ◽  
N. Garry Tarr
Keyword(s):  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
High Speed ◽  
Temperature Range ◽  
Polysilicon Emitters ◽  
The Cost ◽  
Polysilicon Emitter ◽  
Phosphorus Doped

Rapid thermal annealing of in situ phosphorus-doped polysilicon emitter transistors in the temperature range 850–1000 °C greatly reduces the emitter resistance RE at the cost of a slight increase in hole back injection, seen as a decrease in emitter Gummel number GE. Annealing at 1000 °C for 5 s gives low emitter resistance (RE ≈ 100 Ω μm2) while maintaining good suppression of back injection (GE ≥ 1014 scm−4). Annealing at temperatures below 1000 °C fails to reduce RE sufficiently for use in high-speed devices.

Emitter resistance of arsenic- and phosphorus-doped polysilicon emitter transistors

1985 ◽  
Vol 6 (10) ◽  
pp. 516-518 ◽  
Author(s):  
E.F. Chor ◽  
P. Ashburn ◽  
A. Brunnschweiler
Keyword(s):  
Polysilicon Emitter ◽  
Phosphorus Doped
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