Abstract
Advanced packaging technologies continue to enable the semiconductor industry to meet the needs for ever thinner, smaller and faster components required in mobile devices and other high performance applications. However, the increase in chip I/O count, driven by Moore's law, and the ability to produce FinFETs below 10nm have presented numerous additional challenges to the existing advanced packaging processes.
Furthermore, unlike Moore's law, which predicted the number of transistors in a dense integrated circuit to double approximately every two years, advanced packaging is experiencing an alternate “law”; where instead of the number of transistors increasing, it is the number of functions increasing, within the ever decreasing volume constraints of the final product that drives the technology roadmap.
Inevitably, as functionality increases, so does the process complexity and cost. In this very cost sensitive advanced packaging arena, outsourced semiconductor assembly and test suppliers (OSATs) need to compensate by reducing their manufacturing costs. This requires the OSAT to reduce material costs, increase throughput, yield, and look for new ways to reduce the number of process steps.
One of the ways in which the OSATs have reduced the cost of materials is by removing the silicon wafer from back-end processing altogether; using epoxy mold compound (EMC) to create reconstituted wafers, or by using glass carriers. In the case of glass carriers, it is often the case, that the dice are attached face down on the carrier and subsequent processing prevents the front side patterns from being visible from the top side of the composite stack, even with infrared (IR) imaging. In this particular case, an additional lithography “clear out” window is defined in photoresist over the alignment mark so the opaque film can be etched away from the alignment mark, the resist stripped, and the lithography layer reworked. This additional processing is obviously costly and time consuming.
This paper specifically focuses on the concepts, methodology, and performance of a stepper-based photolithography solution that utilizes a photoresist latent image to provide temporary alignment marks for the lithography process, removing the need for the additional patterning and etching steps. This revolutionary system employs a backside camera, to align to die through the carrier. A separate exposure unit, calibrated to the alignment camera center, exposes temporary latent image targets which are then detected by the system's regular alignment system during the normal stepper lithography operation.
The performance data for the alignment, overlay, and latent image depth control are discussed in detail. The final analysis proves that overlay of < 2μm is readily achievable, with no impact on system throughput.
Ultra-precision engineering in lithographic exposure equipment for the semiconductor industry