A 90 nm-CMOS broadband receiver with 10 dB conversion gain and 15 dB noise figure in 80–110 GHz suitable for multi-pixel imaging arrays

2021 ◽  
Vol 92 (8) ◽  
pp. 084703
Author(s):  
Hsuan Chu-Chen ◽  
Kuan-Han Hsieh ◽  
Robert Hu
Keyword(s):  
Noise Figure ◽  
Conversion Gain ◽  
Imaging Arrays

Low Voltage Low Power Up-Conversion Mixer for Wireless Sensor Networks Node Application

2013 ◽  
Vol 760-762 ◽  
pp. 516-520
Author(s):  
Ge Sun ◽  
Zhi Qun Li ◽  
Chen Jian Wu ◽  
Meng Zhang ◽  
Jia Cao ◽  
...  
Keyword(s):  
Wireless Sensor Networks ◽  
Sensor Networks ◽  
Low Power ◽  
Low Voltage ◽  
Noise Figure ◽  
Cmos Technology ◽  
Negative Resistance ◽  
Wireless Sensor ◽  
Operating Voltage ◽  
Conversion Gain

A low voltage, low power up-conversion mixer is presented here for 2.4GHz wireless sensor networks (WSN). It was based on a double-balanced Gilbert cell type. The current-reuse technique was used to reduce the power consumption and negative-resistance compensation technique was used to improve the conversion gain. The mixer was designed in 0.18μm RF CMOS technology, and was simulated with Cadence SpectreRF. The simulation results indicate that the conversion gain is 6.37dB, the noise figure is 15.36dB and the input 1dB compression point is-10.3dBm, while consuming 1mA current for operating voltage at 1V.

scholarly journals 50 MHz–10 GHz Low-Power Resistive Feedback Current-Reuse Mixer with Inductive Peaking for Cognitive Radio Receiver

2014 ◽  
Vol 2014 ◽  
pp. 1-11 ◽  
Author(s):  
Nandini Vitee ◽  
Harikrishnan Ramiah ◽  
Wei-Keat Chong ◽  
Gim-Heng Tan ◽  
Jeevan Kanesan ◽  
...  
Keyword(s):  
Cognitive Radio ◽  
Power Consumption ◽  
Low Power ◽  
Noise Figure ◽  
Cmos Technology ◽  
Radio Receiver ◽  
Conversion Gain ◽  
Current Reuse ◽  
Inductive Peaking ◽  
Resistive Feedback

A low-power wideband mixer is designed and implemented in 0.13 µm standard CMOS technology based on resistive feedback current-reuse (RFCR) configuration for the application of cognitive radio receiver. The proposed RFCR architecture incorporates an inductive peaking technique to compensate for gain roll-off at high frequency while enhancing the bandwidth. A complementary current-reuse technique is used between transconductance and IF stages to boost the conversion gain without additional power consumption by reusing the DC bias current of the LO stage. This downconversion double-balanced mixer exhibits a high and flat conversion gain (CG) of 14.9 ± 1.4 dB and a noise figure (NF) better than 12.8 dB. The maximum input 1-dB compression point (P1dB) and maximum input third-order intercept point (IIP3) are −13.6 dBm and −4.5 dBm, respectively, over the desired frequency ranging from 50 MHz to 10 GHz. The proposed circuit operates down to a supply headroom of 1 V with a low-power consumption of 3.5 mW.

scholarly journals A 30–40 GHz CMOS Receiver Front-End with 5.9 dB NF and 16.5 dB Conversion Gain for Broadband Spectrum Sensing Applications

Electronics ◽  
2019 ◽  
Vol 8 (5) ◽  
pp. 593
Author(s):  
Hyunki Jung ◽  
Dzuhri Radityo Utomo ◽  
Saebyeok Shin ◽  
Seok-Kyun Han ◽  
Sang-Gug Lee ◽  
...  
Keyword(s):  
Spectrum Sensing ◽  
Noise Figure ◽  
Low Noise ◽  
Conversion Gain ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Sensing Applications ◽  
Front End ◽  
Broadband Spectrum ◽  
Down Conversion

A broadband receiver front-end with low noise figure and flat conversion gain response is presented in this paper. The receiver front-end is a part of the broadband spectrum sensing receiver and processes 30–40 GHz of broad input spectrum followed by down-conversion to DC-10 GHz of IF signal. The proposed work is comprised of a low noise amplifier (LNA), on-chip passive Balun, down conversion mixer, and output buffer. To achieve front-end target specification over 10 GHz input bandwidth, the stagger-tuned LNA is employed and the down conversion mixer is loaded with a 3rd-order LC ladder low pass filter. The prototype chip was implemented in 45 nm CMOS technology. The chip achieves 10.3–16.5 dB conversion gain, 5.9 dB integrated NF, and −11 dBm IIP3 from 30 to 40 GHz. The chip is realized within 0.42 mm 2 and consumes 96 mW from a 1.2 V supply.

scholarly journals A Low-Noise, High-Gain, and Small-Size UWB Mixer Utilizing Negative Impedance Technique and Source Input Method

Electronics ◽  
2021 ◽  
Vol 10 (21) ◽  
pp. 2655
Author(s):  
Zhaokun Zhou ◽  
Xiaoran Li ◽  
Xinghua Wang ◽  
Wei Gu
Keyword(s):  
Flicker Noise ◽  
Noise Figure ◽  
Supply Voltage ◽  
High Gain ◽  
Low Noise ◽  
Ultra Wideband ◽  
Conversion Gain ◽  
Chip Area ◽  
Input Method ◽  
Impedance Technique

This paper presents an ultra-wideband (UWB) down-conversion mixer with low-noise, high-gain and small-size. The negative impedance technique and source input method are applied for the proposed mixer. The negative impedance achieves the dynamic current injection and increases the mixer output impedance, which reduces the mixer flicker noise and increases its conversion gain. The source input method allows the input matching networks to be cancelled, avoiding the noise and loss introduced by the matching resistors, saving the chip area occupied by the matching inductors. The proposed mixer is designed in 45-nm SOI process provided by GlobalFoundries. The simulation results show a conversion gain of 11.4–14.3 dB, ranging from 3.1 to 10.6 GHz, a minimum noise figure of 9.8 dB, a RF port return loss of less than −11 dB, a port-to-port isolation of better than −48 dB, and a core chip area of 0.16 × 0.16 mm2. The power consumption from a 1 V supply voltage is 2.85 mW.

scholarly journals 0.5-7.5 GHZ LOW-POWER, INDUCTORLESS CURRENT FOLDED MIXER IN 0.18-μM CMOS FOR BROADBAND APPLICATIONS

2013 ◽  
pp. 112-116
Author(s):  
ZAHRA GHANE FASHTALI ◽  
MAHROKH MAGHSOODI ◽  
REZA EBRAHIMI ATANI ◽  
MEHRGAN MAHDAVI
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Noise Figure ◽  
Cmos Process ◽  
Conversion Gain ◽  
Fully Differential ◽  
Dc Power ◽  
Maximum Conversion ◽  
Cell Topology ◽  
Down Conversion

A fully differential low-power down-conversion mixer using a TSMC 0.18-μm CMOS process is presented in this paper. The proposed mixer is based on a folded double-balanced Gilbert cell topology that enhances conversion gain and reduces power dissipation. Though, this mixer is designed for 5.8 GHz ISM band applications, but at 0.5-7.5 GHz, the proposed mixer exhibits a maximum conversion gain of 12dB, maximum IIP3 of -2.5 dBm, maximum input 1-dB compression point of -13 dBm, the minimum DSB noise figure of 9.2 dB and a dc power consumption of 2.52 mW at 1.8 V power supply. Also, this circuit architecture increases port-to-port isolations to above 140 dB. Moreover this mixer is suitable for broadband applications.

Review of Millimeter-Wave Integrated Circuits With Low Power Consumption for High Speed Wireless Communications

Frequenz ◽  
2017 ◽  
Vol 71 (1-2) ◽  
pp. 1-9
Author(s):  
Frank Ellinger ◽  
David Fritsche ◽  
Gregor Tretter ◽  
Jan Dirk Leufker ◽  
Uroschanit Yodprasit ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Power Consumption ◽  
High Speed ◽  
Noise Figure ◽  
Leading Edge ◽  
Conversion Gain ◽  
60 Ghz ◽  
Radio Frequency Integrated Circuits ◽  
Power Added Efficiency ◽  
Analogue To Digital

Abstract In this paper we review high-speed radio-frequency integrated circuits operating up to 210 GHz and present selected state-of-the-art circuits with leading-edge performance, which we have designed at our chair. The following components are discussed employing bipolar complementary metal oxide semiconductors (BiCMOS) technologies: a 200 GHz amplifier with 17 dB gain and around 9 dB noise figure consuming only 18 mW, a 200 GHz down mixer with 5.5 dB conversion gain and 40 mW power consumption, a 190 GHz receiver with 47 dB conversion gain and 11 dB noise figure and a 60 GHz power amplifier with 24.5 dBm output power and 12.9 % power added efficiency (PAE). Moreover, we report on a single-core flash CMOS analogue-to-digital converter (ADC) with 3 bit resolution and a speed of 24 GS/s. Finally, we discuss a 60 GHz on-off keying (OOK) BiCMOS transceiver chip set. The wireless transmission of data with 5 Gb/s at 42 cm distance between transmitter and receiver was verified by experiments. The complete transceiver consumes 396 mW.

Sign in / Sign up

Export Citation Format

Share Document