scholarly journals A 30–40 GHz CMOS Receiver Front-End with 5.9 dB NF and 16.5 dB Conversion Gain for Broadband Spectrum Sensing Applications

Electronics ◽  
2019 ◽  
Vol 8 (5) ◽  
pp. 593
Author(s):  
Hyunki Jung ◽  
Dzuhri Radityo Utomo ◽  
Saebyeok Shin ◽  
Seok-Kyun Han ◽  
Sang-Gug Lee ◽  
...  
Keyword(s):  
Spectrum Sensing ◽  
Noise Figure ◽  
Low Noise ◽  
Conversion Gain ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Sensing Applications ◽  
Front End ◽  
Broadband Spectrum ◽  
Down Conversion

A broadband receiver front-end with low noise figure and flat conversion gain response is presented in this paper. The receiver front-end is a part of the broadband spectrum sensing receiver and processes 30–40 GHz of broad input spectrum followed by down-conversion to DC-10 GHz of IF signal. The proposed work is comprised of a low noise amplifier (LNA), on-chip passive Balun, down conversion mixer, and output buffer. To achieve front-end target specification over 10 GHz input bandwidth, the stagger-tuned LNA is employed and the down conversion mixer is loaded with a 3rd-order LC ladder low pass filter. The prototype chip was implemented in 45 nm CMOS technology. The chip achieves 10.3–16.5 dB conversion gain, 5.9 dB integrated NF, and −11 dBm IIP3 from 30 to 40 GHz. The chip is realized within 0.42 mm 2 and consumes 96 mW from a 1.2 V supply.

A Low-Power, High-Gain, and Low-Noise 802.11a Down-Conversion Mixer in 0.35-μm SiGe Bi-CMOS Technology

2017 ◽  
Vol 26 (09) ◽  
pp. 1750134 ◽  
Author(s):  
Jun-Da Chen ◽  
Song-Hao Wang
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Supply Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
Cmos Process ◽  
Conversion Gain ◽  
Dc Power ◽  
Down Conversion

The paper presents a novel 5.15[Formula: see text]GHz–5.825[Formula: see text]GHz SiGe Bi-CMOS down-conversion mixer for WLAN 802.11a receiver. The architecture used is based on Gilbert cell mixer, the combination of MOS transistors and HBT BJT transistor device characteristics. The hetero-junction bipolar transistor (HBT) topology is adopted at the transconductance stage to improve power gain and reduce noise factor, and the LO series-parallel CMOS switch topology will be applied to reduce supply voltage and dc power at the switching stage. This mixer is implemented in TSMC 0.35-[Formula: see text]m SiGe Bi-CMOS process, and the chip size including the test pads is 1.175*0.843[Formula: see text]mm2. The main advantages for the proposed mixer are high conversion gain, a moderate linearity, low noise figure, and low power. The post-simulation results achieved are as follows: 14[Formula: see text]dB power conversion gain, [Formula: see text]6[Formula: see text]dBm input third-order intercept point (IIP3), 6.85[Formula: see text]dB double side band (DSB) noise figure. The total mixer current is about 1.54[Formula: see text]mA from 1.4[Formula: see text]V supply voltage including output buffer. The total dc power consumption is 2.15[Formula: see text]mW.

scholarly journals Methods of structural and functional implementation of ultra-wide range receiving paths

Doklady BGUIR ◽  
2020 ◽  
Vol 18 (7) ◽  
pp. 23-30
Author(s):  
D. V. Arkhipenkov ◽  
I. I. Zabenkov ◽  
S. S. Salanovich
Keyword(s):  
Dynamic Range ◽  
Noise Figure ◽  
Low Noise ◽  
Radio Receiver ◽  
Monitoring Systems ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Radio Monitoring ◽  
Wide Range ◽  
Element Base

Currently, radio monitoring systems are being actively improved in the direction of expanding the range of operating frequencies and the width of the spectrum of processed signals, which in some cases requires changing approaches to the design of their receiving devices. The purpose of the article is to substantiate the methods and circuit design options for implementing a receiver of an ultra-wide-range radio monitoring system and to justify the sequence of selecting the element base and calculating the parameters of the receiving path. The research proves expedient to choose the infradine structure of the radio receiving path as a basis, in which the frequency of the mirror channel is located far from the frequency of the main channel, so the mirror channel is easily suppressed by a simple low-pass filter. One of the main problems that arise when designing ultra-wideband radio receivers is the simultaneous provision of a large dynamic range and a low noise figure. To reduce the noise figure, a variant of constructing a path was proposed, starting with a low-noise amplifier with increased parameters of nonlinear selectivity, which is acceptable if there is a low probability of intermodulation combinations. The article suggests a receiver with an operating frequency range of 0.5–18 GHz and an analogto-digital converter with a speed of up to 10.4 GSPS. The element base was selected for the receiving devices and the main parameters of the path were calculated. A number of examples are used to analyze the ways to increase the dynamic range of a radio receiver and the influence of element base parameters on the device performance. The main technical characteristics of the radio receiver for effective operation of modern radio monitoring systems and the ways to increase the dynamic range thereof are described.

scholarly journals A 219–266 GHz LO-tunable direct-conversion IQ receiver module in a SiGe HBT technology

2018 ◽  
Vol 10 (5-6) ◽  
pp. 587-595 ◽  
Author(s):  
P. Rodriguez Vazquez ◽  
J. Grzyb ◽  
N. Sarmah ◽  
B. Heinemann ◽  
U.R. Pfeiffer
Keyword(s):  
High Speed ◽  
Printed Circuit Board ◽  
Noise Figure ◽  
Direct Conversion ◽  
Circuit Board ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Receiver Module ◽  
On Chip ◽  
Down Conversion

AbstractThis paper presents a fully-integrated direct-conversion fundamentally-operated mixer-first quadrature receiver module with a tunable LO in the 219–266 GHz band. It has been implemented in a 0.13-μm SiGe heterojunction bipolar transistor technology. It includes an on-chip LO path driven externally from the printed circuit board (PCB) connector level at 13.6–16.7 GHz. A hybrid coupler generates the quadrature LO signal, which drives a pair of double-balanced fundamentally-operated down-conversion mixers, whose RF ports are connected to a wideband lens-integrated on-chip ring antenna. The chip-on-lens assembly is placed in the recess of a high-speed PCB and wire-bonded. To compensate the inductive behavior of the wire-bond interconnection between the chip and the PCB at the high-speed IF outputs, an on-board 8-section step-impedance low-pass filter has been implemented. The module shows a 47 GHz 3-dB radio frequency/local oscillator operation bandwidth (BW), a peak conversion gain of 7.8 dB, a single-side-band noise figure of 11.3 dB, and a 3-dB IF BW of 13 GHz. The in-phase and quadrature amplitude imbalance stays below 1.58 dB for the 210–280 GHz band. The down-conversion and the baseband stages consume together 75.5 mW, while the LO path 378 mW. The maximum data-rate achieved with this receiver in combination with the transmitter presented in [1–3] is 60 Gbps for quadrature phase shift keying modulation.

scholarly journals Wideband Reconfigurable Integrated Low-Pass Filter for 5G Compatible Software Defined Radio Solutions

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 734
Author(s):  
Karolis Kiela ◽  
Marijan Jurgo ◽  
Vytautas Macaitis ◽  
Romualdas Navickas
Keyword(s):  
Software Defined Radio ◽  
Dynamic Range ◽  
Noise Figure ◽  
Harmonic Distortion ◽  
Cmos Process ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Filter Performance ◽  
Low Pass ◽  
Bandwidth Tuning

This article presents a wideband reconfigurable integrated low-pass filter (LPF) for 5G NR compatible software-defined radio (SDR) solutions. The filter uses Active-RC topology to achieve high linearity performance. Its bandwidth can be tuned from 2.5 MHz to 200 MHz, which corresponds to a tuning ratio of 92.8. The order of the filter can be changed between the 2nd, 4th, or 6th order; it has built-in process, voltage, and temperature (PVT) compensation with a tuning range of ±42%; and power management features for optimization of the filter performance across its entire range of bandwidth tuning. Across its entire order, bandwidth, and power configuration range, the filter achieves in-band input-referred third-order intercept point (IIP3) between 32.7 dBm and 45.8 dBm, spurious free dynamic range (SFDR) between 63.6 dB and 79.5 dB, 1 dB compression point (P1dB) between 9.9 dBm and 14.1 dBm, total harmonic distortion (THD) between −85.6 dB and −64.5 dB, noise figure (NF) between 25.9 dB and 31.8 dB and power dissipation between 1.19 mW and 73.4 mW. The LPF was designed and verified using 65 nm CMOS process; it occupies a 0.429 mm2 area of silicon and uses a 1.2 V supply.

scholarly journals A Four-Channel Low-Noise Readout IC for Air Flow Measurement Using Hot Wire Anemometer in 0.18 μm CMOS Technology

Sensors ◽  
2021 ◽  
Vol 21 (14) ◽  
pp. 4694
Author(s):  
Kyeongsik Nam ◽  
Hyungseup Kim ◽  
Yongsu Kwon ◽  
Gyuri Choi ◽  
Taeyup Kim ◽  
...  
Keyword(s):  
Supply Voltage ◽  
Air Flow ◽  
Low Noise ◽  
Cmos Process ◽  
Significant Information ◽  
Flow Measurements ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Op Amp ◽  
Noise Characteristics

Air flow measurements provide significant information required for understanding the characteristics of insect movement. This study proposes a four-channel low-noise readout integrated circuit (IC) in order to measure air flow (air velocity), which can be beneficial to insect biomimetic robot systems that have been studied recently. Instrumentation amplifiers (IAs) with low-noise characteristics in readout ICs are essential because the air flow of an insect’s movement, which is electrically converted using a microelectromechanical systems (MEMS) sensor, generally produces a small signal. The fundamental architecture employed in the readout IC is a three op amp IA, and it accomplishes low-noise characteristics by chopping. Moreover, the readout IC has a four-channel input structure and implements an automatic offset calibration loop (AOCL) for input offset correction. The AOCL based on the binary search logic adjusts the output offset by controlling the input voltage bias generated by the R-2R digital-to-analog converter (DAC). The electrically converted air flow signal is amplified using a three op amp IA, which is passed through a low-pass filter (LPF) for ripple rejection that is generated by chopping, and converted to a digital code by a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC). Furthermore, the readout IC contains a low-dropout (LDO) regulator that enables the supply voltage to drive digital circuits, and a serial peripheral interface (SPI) for digital communication. The readout IC is designed with a 0.18 μm CMOS process and the current consumption is 1.886 mA at 3.3 V supply voltage. The IC has an active area of 6.78 mm2 and input-referred noise (IRN) characteristics of 95.4 nV/√Hz at 1 Hz.

scholarly journals A 1.5–40 GHz frequency modulated continuous wave radar receiver front-end

2021 ◽  
pp. 1-11
Author(s):  
Mantas Sakalas ◽  
Niko Joram ◽  
Frank Ellinger
Keyword(s):  
Continuous Wave ◽  
Noise Figure ◽  
Supply Voltage ◽  
Low Noise ◽  
Ultra Wideband ◽  
Front End ◽  
Wave Radar ◽  
Bicmos Technology ◽  
Circuit Components ◽  
High Band

Abstract This study presents an ultra-wideband receiver front-end, designed for a reconfigurable frequency modulated continuous wave radar in a 130 nm SiGe BiCMOS technology. A variety of innovative circuit components and design techniques were employed to achieve the ultra-wide bandwidth, low noise figure (NF), good linearity, and circuit ruggedness to high input power levels. The designed front-end is capable of achieving 1.5–40 GHz bandwidth, 30 dB conversion gain, a double sideband NF of 6–10.7 dB, input return loss better than 7.5 dB and an input referred 1 dB compression point of −23 dBm. The front-end withstands continuous wave power levels of at least 25 and 20 dBm at low band and high band inputs respectively. At 3 V supply voltage, the DC power consumption amounts to 302 mW when the low band is active and 352 mW for the high band case, whereas the total IC size is $3.08\, {\rm nm{^2}}$ .

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