Nitrogen-induced ultralow power switching in flexible ZnO-based memristor for artificial synaptic learning

2021 ◽  
Vol 118 (10) ◽  
pp. 103502
Author(s):  
Ya Lin ◽  
Jilin Liu ◽  
Jiajuan Shi ◽  
Tao Zeng ◽  
Xuanyu Shan ◽  
...  
Keyword(s):  
Power Switching ◽  
Ultralow Power ◽  
Synaptic Learning

Ultralow power switching of Ta2O5/AlOX bilayer synergistic resistive random access memory

2020 ◽  
Vol 53 (33) ◽  
pp. 335104
Author(s):  
Chuang Li ◽  
Fang Wang ◽  
Kai Hu ◽  
Wenxi Li ◽  
Jinshi Zhao ◽  
...  
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Resistive Random Access Memory ◽  
Access Memory ◽  
Power Switching ◽  
Ultralow Power

Ultralow power switching in a silicon-rich SiNy/SiNx double-layer resistive memory device

2017 ◽  
Vol 19 (29) ◽  
pp. 18988-18995 ◽  
Author(s):  
Sungjun Kim ◽  
Yao-Feng Chang ◽  
Min-Hwi Kim ◽  
Suhyun Bang ◽  
Tae-Hyeon Kim ◽  
...  
Keyword(s):  
Low Power ◽  
Double Layer ◽  
Resistive Switching ◽  
Layered Structure ◽  
Memory Device ◽  
Resistive Memory ◽  
Power Switching ◽  
Ultralow Power

Here we demonstrate low-power resistive switching in a Ni/SiNy/SiNx/p++-Si device by proposing a double-layered structure (SiNy/SiNx), where the two SiN layers have different trap densities.

Tunable, Ultralow-Power Switching in Memristive Devices Enabled by a Heterogeneous Graphene-Oxide Interface

2014 ◽  
Vol 26 (20) ◽  
pp. 3275-3281 ◽  
Author(s):  
Min Qian ◽  
Yiming Pan ◽  
Fengyuan Liu ◽  
Miao Wang ◽  
Haoliang Shen ◽  
...  
Keyword(s):  
Graphene Oxide ◽  
Oxide Interface ◽  
Power Switching ◽  
Ultralow Power

Study of SiC Device for Pulsed Power Switching Circuit

2019 ◽  
Vol 139 (8) ◽  
pp. 345-350
Author(s):  
Toru Tagawa ◽  
Tomohiko Yamashita ◽  
Takashi Sakugawa ◽  
Sunao Katsuki ◽  
Kenzi Hukuda ◽  
...  
Keyword(s):  
Pulsed Power ◽  
Switching Circuit ◽  
Power Switching

Ultralow-Power and Secure S-Box Circuit Using FinFET Based ECRL Adiabatic Logic

2018 ◽  
Vol 10 (3) ◽  
Author(s):  
K. Srilakshmi ◽  
◽  
A. V. N. Tilak ◽  
K. Srinivasa Rao ◽  
◽  
...  
Keyword(s):  
Adiabatic Logic ◽  
Ultralow Power

Thermal-aware Output Polarity Selection Based on And-Inverter Graph Manipulation

2019 ◽  
Vol 12 (1) ◽  
pp. 30-39 ◽  
Author(s):  
Apangshu Das ◽  
Sambhu Nath Pradhan
Keyword(s):  
Integrated Circuits ◽  
Power Density ◽  
Logic Synthesis ◽  
Programmable Logic Arrays ◽  
Power Switching ◽  
Nsga Ii ◽  
Multi Level ◽  
Search Approach ◽  
Efficient Power ◽  
The Impact

Background: Output polarity of the sub-function is generally considered to reduce the area and power of a circuit at the two-level realization. Along with area and power, the power-density is also one of the significant parameter which needs to be consider, because power-density directly converges to circuit temperature. More than 50% of the modern day integrated circuits are damaged due to excessive overheating. Methods: This work demonstrates the impact of efficient power density based logic synthesis (in the form of suitable polarity selection of sub-function of Programmable Logic Arrays (PLAs) for its multilevel realization) for the reduction of temperature. Two-level PLA optimization using output polarity selection is considered first and compared with other existing techniques and then And-Invert Graphs (AIG) based multi-level realization has been considered to overcome the redundant solution generated in two-level synthesis. AIG nodes and associated power dissipation can be reduced by rewriting, refactoring and balancing technique. Reduction of nodes leads to the reduction of the area but on the contrary increases power and power density of the circuit. A meta-heuristic search approach i.e., Nondominated Sorting Genetic Algorithm-II (NSGA-II) is proposed to select the suitable output polarity of PLA sub-functions for its optimal realization. Results: Best power density based solution saves up to 8.29% power density compared to ‘espresso – dopo’ based solutions. Around 9.57% saving in area and 9.67% saving in power (switching activity) are obtained with respect to ‘espresso’ based solution using NSGA-II. Conclusion: Suitable output polarity realized circuit is converted into multi-level AIG structure and synthesized to overcome the redundant solution at the two-level circuit. It is observed that with the increase in power density, the temperature of a particular circuit is also increases.

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