scholarly journals Channel geometry-dependent threshold voltage and transconductance degradation in gate-all-around nanosheet junctionless transistors

AIP Advances ◽  
2021 ◽  
Vol 11 (5) ◽  
pp. 055111
Author(s):  
Dae-Young Jeon
Keyword(s):  
Threshold Voltage ◽  
Channel Geometry ◽  
Junctionless Transistors

scholarly journals Analysis of an Approximated Model for the Depletion Region Width of Planar Junctionless Transistors

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1436
Author(s):  
Arian Nowbahari ◽  
Avisek Roy ◽  
Muhammad Nadeem Akram ◽  
Luca Marchetti
Keyword(s):  
Numerical Simulations ◽  
Analytical Model ◽  
Threshold Voltage ◽  
Analytical Formula ◽  
Numerical Data ◽  
Maximum Error ◽  
Depletion Region ◽  
Comsol Multiphysics ◽  
Flat Band ◽  
Junctionless Transistors

In this paper, we investigate the accuracy of the approximated analytical model currently utilized, by many researchers, to describe the depletion region width in planar junctionless transistors (PJLT). The proposed analysis was supported by numerical simulations performed in COMSOL Multiphysics software. By comparing the numerical results and the approximated analytical model of the depletion region width, we calculated that the model introduces a maximum RMS error equal to 90 % of the donor concentration in the substrate. The maximum error is achieved when the gate voltage approaches the threshold voltage ( V t h ) or when it approaches the flat band voltage ( V F B ) of the transistor. From these results, we concluded that this model cannot be used to determine accurately the flat-band and the threshold voltage of the transistor, although it represents a straightforward method to estimate the depletion region width in PJLT. By using the approximated analytical model, we extracted an analytical formula, which describes the electron concentration at the ideal boundary of the depletion region. This formula approximates the numerical data extracted from COMSOL with a relative error lower than 1 % . The proposed formula is in our opinion, as useful as the formula of the approximated analytical model because it allows for estimating the position of the depletion region also when the drain and source terminals are not grounded. We concluded that the analytical formula proposed at the end of this work could be useful to determine the position of the depletion region boundary in numerical simulations and in graphical representations provided by COMSOL Multiphysics software.

Sensitivity of Threshold Voltage to Nanowire Width Variation in Junctionless Transistors

2011 ◽  
Vol 32 (2) ◽  
pp. 125-127 ◽  
Author(s):  
Sung-Jin Choi ◽  
Dong-Il Moon ◽  
Sungho Kim ◽  
Juan P. Duarte ◽  
Yang-Kyu Choi
Keyword(s):  
Threshold Voltage ◽  
Junctionless Transistors

Geometry Effect on the Electrokinetic Instability of the Electroosmotic Flow in Microfluidic Channels

2008 ◽  
Author(s):  
Yee Cheong Lam ◽  
Gongyue Tang ◽  
Deguang Yan
Keyword(s):  
Threshold Voltage ◽  
Electroosmotic Flow ◽  
Fluorescent Imaging ◽  
Microfluidic Channels ◽  
Channel Geometry ◽  
Electrolyte Conductivity ◽  
Electrokinetic Instability ◽  
Micro Channels ◽  
Onset Voltage ◽  
Abrupt Contraction

To study the effect of geometry on electroosmotic flow in micro channels, we fabricated PDMS-glass microchannels of different designs, which have patterned channels with abrupt contraction of different sizes. Using fluorescent imaging technology, we demonstrated the effect of geometry on the instability of DC driven electroosmotic flow in microfluidic channels. For certain geometry and conductivity of the electrolyte solution (Sodium Bicarbonate), there is a threshold voltage for electroosmotic instability, exhibiting itself as “ripple”. Generally, the factors which affect the threshold voltage include channel width, channel geometry, and electrolyte conductivity. Narrower channel resulted in higher onset voltage. As conductivity of the electrolyte increases, the threshold voltage tends to increase. Early transition to unstable electroosmotic flow in microfluidic channels was observed under relatively low Re.

Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations

2009 ◽  
Vol E92-A (4) ◽  
pp. 990-997
Author(s):  
Takaaki OKUMURA ◽  
Atsushi KUROKAWA ◽  
Hiroo MASUDA ◽  
Toshiki KANAMOTO ◽  
Masanori HASHIMOTO ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Time Variation ◽  
Transition Time ◽  
Computational Accuracy

Analysis Approach on DMOS Transistor Vth Mismatch Due to Trapped Charges

2015 ◽  
Author(s):  
Hashim Ismail ◽  
Ang Chung Keow ◽  
Kenny Gan Chye Siong
Keyword(s):  
Failure Analysis ◽  
Threshold Voltage ◽  
Gate Oxide ◽  
Analysis Approach ◽  
Test Results ◽  
Root Cause ◽  
Switching Event ◽  
Output Transistor ◽  
Event Based ◽  
Trapped Charge

Abstract An output switching malfunction was reported on a bridge driver IC. The electrical verification testing revealed evidence of an earlier over current condition resulting from an abnormal voltage sense during a switching event. Based on these test results, we developed the hypothesis that a threshold voltage mismatch existed between the sense transistor and the output transistor. This paper describes the failure analysis approach we used to characterize the threshold voltage mismatch as well as our approach to determine the root cause, which was trapped charge on the gate oxide of the sense transistor.

Analysis of an Anomalous CMOS Transistor Exhibiting Drain to Source Leakage—Its Model and Cause

2014 ◽  
Author(s):  
Yuk L. Tsang ◽  
Alex VanVianen ◽  
Xiang D. Wang ◽  
N. David Theodore
Keyword(s):  
Threshold Voltage ◽  
Crystalline Silicon ◽  
Electrical Characterization ◽  
Visual Defect ◽  
Scanning Capacitance Microscopy ◽  
Device Model ◽  
Graphical Simulation ◽  
Cmos Transistor

Abstract In this paper, we report a device model that has successfully described the characteristics of an anomalous CMOS NFET and led to the identification of a non-visual defect. The model was based on detailed electrical characterization of a transistor exhibiting a threshold voltage (Vt) of about 120mv lower than normal and also exhibiting source to drain leakage. Using a simple graphical simulation, we predicted that the anomalous device was a transistor in parallel with a resistor. It was proposed that the resistor was due to a counter doping defect. This was confirmed using Scanning Capacitance Microscopy (SCM). The dopant defect was shown by TEM imaging to be caused by a crystalline silicon dislocation.

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