Short-channel robustness from negative capacitance in 2D NC-FETs

2021 ◽  
Vol 118 (10) ◽  
pp. 101903
Author(s):  
Yuh-Chen Lin ◽  
G. Bruce Rayner ◽  
Jorge Cardenas ◽  
Aaron D. Franklin
2018 ◽  
Vol 57 (4S) ◽  
pp. 04FD03 ◽  
Author(s):  
Hiroyuki Ota ◽  
Junichi Hattori ◽  
Hidehiro Asai ◽  
Tsutomu Ikegami ◽  
Koichi Fukuda ◽  
...  

2016 ◽  
Vol 37 (1) ◽  
pp. 111-114 ◽  
Author(s):  
Asif Islam Khan ◽  
Korok Chatterjee ◽  
Juan Pablo Duarte ◽  
Zhongyuan Lu ◽  
Angada Sachid ◽  
...  

2021 ◽  
Author(s):  
Shih-En Huang ◽  
Pin Su ◽  
Chenming Hu

<div>In this work, we report that the AFE/FE gate-stack can be utilized to engineer the S-curve for boosting the I<sub>ON</sub> of NC-FinFET. By using a short-channel BSIM-CMG compatible AFE/FE stack NC-FinFET model, the capacitance matching and ON-state performance for AFE/FE stack NC-FinFETs are investigated. Our study indicates that, the AFE/FE gate-stack can be used to improve the capacitance matching in strong inversion at higher gate-bias. Therefore, impressively higher ON-state current (compared to single-layer) can be achieved. In reality, source-drain series resistance will make such high IDS impractical. The more likely strategy is to use lower V<sub>DD</sub> to achieve much lower power consumption (and reduced vertical fields). While the transient NC effect also needs to be carefully investigated, this study suggests significant long term benefits to V<sub>DD</sub> scaling if materials with certain AFE and FE properties are developed and introduced in IC manufacturing in the future.</div>


Nanoscale ◽  
2018 ◽  
Vol 10 (40) ◽  
pp. 19131-19139 ◽  
Author(s):  
Meng Su ◽  
Xuming Zou ◽  
Youning Gong ◽  
Jianlu Wang ◽  
Yuan Liu ◽  
...  

Nanowire based NC-FETs with SS values below 60 mV dec−1 are demonstrated. Short channel devices are fabricated using a self-alignment approach.


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