scholarly journals Gunn threshold voltage characterization in GaAs devices with wedge-shaped tapering

2020 ◽  
Vol 128 (7) ◽  
pp. 074502
Author(s):  
Hua-Wei Hsu ◽  
Michael J. Dominguez ◽  
Vanessa Sih
Keyword(s):  
Threshold Voltage ◽  
Gaas Devices

Prospects for GaAs-on-Si LSI Circuits

1987 ◽  
Vol 91 ◽  
Author(s):  
H. Shichijo ◽  
L.T. Tran ◽  
R.J. Matyi ◽  
J.W. Lee
Keyword(s):  
Threshold Voltage ◽  
Large Scale ◽  
Recent Progress ◽  
Ring Oscillators ◽  
Standard Process ◽  
Bulk Gaas ◽  
Gaas On Si ◽  
Recent Success ◽  
Bipolar Devices ◽  
Gaas Devices

ABSTRACTThis paper will review some of the recent progress in GaAs-on-Si devices and circuits, and discuss the issues involved in realizing large scale ICs in GaAs-on-Si wafers. With a recent success in fabricating 1 Kbit static RAMs in GaAs-on-Si wafers, it has become apparent that this material is indeed acceptable for LSI complexity circuits. GaAs MESFETs fabricated using a standard process show an excellent threshold voltage uniformity which is comparable to that for bulk GaAs devices. GaAs bipolar devices on GaAs-on-Si have realized a gain of 25 which is the highest reported for bipolar devices in GaAs-on-Si material. Bipolar ring oscillators and 256-bit ROMs consisting of more than 100 gates have also been realized. In spite of these successes, however, there are numerous issues that need to be solved before this material becomes practical.

Using the secondary electrons (SE) of SEM with NIST‘s MONSEL-II program to obtain improved linewidth measurements and slope angles of line edges on a MMIC GaAs device

1996 ◽  
Vol 54 ◽  
pp. 944-945
Author(s):  
Richard G. Sartore
Keyword(s):  
Integrated Circuits ◽  
Plasma Etching ◽  
Microwave Integrated Circuits ◽  
Monolithic Microwave Integrated Circuits ◽  
Thick Gold ◽  
Gaas Devices ◽  
Source Distance ◽  
Margin Of Error ◽  
Dimensional Measurements ◽  
Barrier Metal

In the evaluation of GaAs devices from the MMIC (Monolithic Microwave Integrated Circuits) program for Army applications, there was a requirement to obtain accurate linewidth measurements on the nominal 0.5 micrometer gate lengths used to fabricate these devices. Preliminary measurements indicated a significant variation (typically 10 % to 30% but could be more) in the critical dimensional measurements of the gate length, gate to source distance and gate to drain distance. Passivation introduced a margin of error, which was removed by plasma etching. Additionally, the high aspect ratio (4-5) of the thick gold (Au) conductors also introduced measurement difficulties. The final measurements were performed after the thick gold conductor was removed and only the barrier metal remained, which was approximately 250 nanometer thick platinum on GaAs substrate. The thickness was measured using the penetration voltage method. Linescan of the secondary electron signal as it scans across the gate is shown in Figure 1.

Fabrication of GaAs Devices

2005 ◽  
Author(s):  
A. Baca ◽  
C. Ashby
Keyword(s):  
Gaas Devices

Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations

2009 ◽  
Vol E92-A (4) ◽  
pp. 990-997
Author(s):  
Takaaki OKUMURA ◽  
Atsushi KUROKAWA ◽  
Hiroo MASUDA ◽  
Toshiki KANAMOTO ◽  
Masanori HASHIMOTO ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Time Variation ◽  
Transition Time ◽  
Computational Accuracy

Analysis Approach on DMOS Transistor Vth Mismatch Due to Trapped Charges

2015 ◽  
Author(s):  
Hashim Ismail ◽  
Ang Chung Keow ◽  
Kenny Gan Chye Siong
Keyword(s):  
Failure Analysis ◽  
Threshold Voltage ◽  
Gate Oxide ◽  
Analysis Approach ◽  
Test Results ◽  
Root Cause ◽  
Switching Event ◽  
Output Transistor ◽  
Event Based ◽  
Trapped Charge

Abstract An output switching malfunction was reported on a bridge driver IC. The electrical verification testing revealed evidence of an earlier over current condition resulting from an abnormal voltage sense during a switching event. Based on these test results, we developed the hypothesis that a threshold voltage mismatch existed between the sense transistor and the output transistor. This paper describes the failure analysis approach we used to characterize the threshold voltage mismatch as well as our approach to determine the root cause, which was trapped charge on the gate oxide of the sense transistor.

Analysis of an Anomalous CMOS Transistor Exhibiting Drain to Source Leakage—Its Model and Cause

2014 ◽  
Author(s):  
Yuk L. Tsang ◽  
Alex VanVianen ◽  
Xiang D. Wang ◽  
N. David Theodore
Keyword(s):  
Threshold Voltage ◽  
Crystalline Silicon ◽  
Electrical Characterization ◽  
Visual Defect ◽  
Scanning Capacitance Microscopy ◽  
Device Model ◽  
Graphical Simulation ◽  
Cmos Transistor

Abstract In this paper, we report a device model that has successfully described the characteristics of an anomalous CMOS NFET and led to the identification of a non-visual defect. The model was based on detailed electrical characterization of a transistor exhibiting a threshold voltage (Vt) of about 120mv lower than normal and also exhibiting source to drain leakage. Using a simple graphical simulation, we predicted that the anomalous device was a transistor in parallel with a resistor. It was proposed that the resistor was due to a counter doping defect. This was confirmed using Scanning Capacitance Microscopy (SCM). The dopant defect was shown by TEM imaging to be caused by a crystalline silicon dislocation.

Analysis of an Anomalous Transistor Exhibiting Dual-Vt Characteristics and Its Cause in a 90nm Node CMOS Technology

2012 ◽  
Author(s):  
Yuk L. Tsang ◽  
Xiang D. Wang ◽  
Reyhan Ricklefs ◽  
Jason Goertz
Keyword(s):  
Threshold Voltage ◽  
Electrical Characterization ◽  
Cmos Technology ◽  
Short Channel ◽  
Visual Defect ◽  
Subthreshold Region ◽  
Short Channel Effect ◽  
Channel Effect ◽  
Transistor Model

Abstract In this paper, we report a transistor model that has successfully led to the identification of a non visual defect. This model was based on detailed electrical characterization of a MOS NFET exhibiting a threshold voltage (Vt) of just about 40mv lower than normal. This small Vt delta was based on standard graphical extrapolation method in the usual linear Id-Vg plots. We observed, using a semilog plot, two slopes in the Id-Vg curves with Vt delta magnified significantly in the subthreshold region. The two slopes were attributed to two transistors in parallel with different Vts. We further found that one of the parallel transistors had short channel effect due to a punch-through mechanism. It was proposed and ultimately confirmed the cause was due to a dopant defect using scanning capacitance microscopy (SCM) technique.

High-current recessed gate enhancement-mode ultrawide bandgap Al x Ga1−x N channel MOSHFET with drain current 0.48 A mm−1 and threshold voltage +3.6 V

2021 ◽  
Vol 14 (1) ◽  
pp. 014003
Author(s):  
Shahab Mollah ◽  
Kamal Hussain ◽  
Abdullah Mamun ◽  
Mikhail Gaevski ◽  
Grigory Simin ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Drain Current ◽  
High Current ◽  
Enhancement Mode ◽  
Recessed Gate
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