Multilevel conductance state in chemical vapor deposited WS2 based resistive memory device

2019 ◽  
Author(s):  
Ujjal Das ◽  
Barnali Mahato ◽  
Anwesha Mahapatra ◽  
Pranab Kumar Sarkar ◽  
Asim Roy
2016 ◽  
Vol 2016 ◽  
pp. 1-6 ◽  
Author(s):  
W. J. Liu ◽  
L. Chen ◽  
P. Zhou ◽  
Q. Q. Sun ◽  
H. L. Lu ◽  
...  

We demonstrated a flash memory device with chemical-vapor-deposited graphene as a charge trapping layer. It was found that the average RMS roughness of block oxide on graphene storage layer can be significantly reduced from 5.9 nm to 0.5 nm by inserting a seed metal layer, which was verified by AFM measurements. The memory window is 5.6 V for a dual sweep of ±12 V at room temperature. Moreover, a reduced hysteresis at the low temperature was observed, indicative of water molecules or −OH groups between graphene and dielectric playing an important role in memory windows.


Author(s):  
L. J. Chen ◽  
L. S. Hung ◽  
J. W. Mayer

When an energetic ion penetrates through an interface between a thin film (of species A) and a substrate (of species B), ion induced atomic mixing may result in an intermixed region (which contains A and B) near the interface. Most ion beam mixing experiments have been directed toward metal-silicon systems, silicide phases are generally obtained, and they are the same as those formed by thermal treatment.Recent emergence of silicide compound as contact material in silicon microelectronic devices is mainly due to the superiority of the silicide-silicon interface in terms of uniformity and thermal stability. It is of great interest to understand the kinetics of the interfacial reactions to provide insights into the nature of ion beam-solid interactions as well as to explore its practical applications in device technology.About 500 Å thick molybdenum was chemical vapor deposited in hydrogen ambient on (001) n-type silicon wafer with substrate temperature maintained at 650-700°C. Samples were supplied by D. M. Brown of General Electric Research & Development Laboratory, Schenectady, NY.


Author(s):  
L. M. Gignac ◽  
K. P. Rodbell

As advanced semiconductor device features shrink, grain boundaries and interfaces become increasingly more important to the properties of thin metal films. With film thicknesses decreasing to the range of 10 nm and the corresponding features also decreasing to sub-micrometer sizes, interface and grain boundary properties become dominant. In this regime the details of the surfaces and grain boundaries dictate the interactions between film layers and the subsequent electrical properties. Therefore it is necessary to accurately characterize these materials on the proper length scale in order to first understand and then to improve the device effectiveness. In this talk we will examine the importance of microstructural characterization of thin metal films used in semiconductor devices and show how microstructure can influence the electrical performance. Specifically, we will review Co and Ti silicides for silicon contact and gate conductor applications, Ti/TiN liner films used for adhesion and diffusion barriers in chemical vapor deposited (CVD) tungsten vertical wiring (vias) and Ti/AlCu/Ti-TiN films used as planar interconnect metal lines.


2019 ◽  
Vol 3 (1) ◽  
Author(s):  
Xibiao Ren ◽  
Jichen Dong ◽  
Peng Yang ◽  
Jidong Li ◽  
Guangyuan Lu ◽  
...  

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