Design of Al2O3/SiO2 laminated stacks with multiple interface dipole layers to achieve large flatband voltage shifts of MOS capacitors

2017 ◽  
Vol 110 (10) ◽  
pp. 102106 ◽  
Author(s):  
Hironobu Kamata ◽  
Koji Kita
Keyword(s):  
Mos Capacitors ◽  
Interface Dipole ◽  
Flatband Voltage ◽  
Multiple Interface

Charge-Transfer Dipoles at the Si-SiO2 Interface and the Metal-Semiconductor Worfunction Difference In Mos Devices.

1987 ◽  
Vol 105 ◽  
Author(s):  
Hisham Z. Massoud
Keyword(s):  
Dipole Moment ◽  
Charge Transfer ◽  
Dipole Moments ◽  
Silicon Substrates ◽  
Interface Dipole ◽  
Mos Devices ◽  
Flatband Voltage ◽  
The Difference ◽  
Definition Of ◽  
Mos Structures

AbstractThe magnitude of the dipole moment at the Si-SiO2 interface resulting from partial charge transfer that takes place upon the formation of interface bonds has been calculated. The charge transfer occurs because of the difference in electronegativity between silicon atoms and SiO2 molecules which are present across the interface. Results obtained for (100) and (111) silicon substrates indicate that the magnitude of the interface dipole moment is dependent on substrate orientation and the interface chemistry. Dipole moments at the Si-SiO2 and gate-SiO2 interfaces should be included in the definition of the flatband voltage VFB of MOS structures. CV-based measurements of the metal-semiconductor workfunction difference φms on (100) and (111) silicon oxidized in dry oxygen and metallized with Al agree with the predictions of this model. Other types of interface dipoles and their processing dependence are briefly discussed.

Analysis of 3-Dimensional 4H-SiC MOS Capacitors Grown by Atomic Layer Deposition of Al2O3

2018 ◽  
Vol 924 ◽  
pp. 490-493 ◽  
Author(s):  
Muhammad I. Idris ◽  
Nick G. Wright ◽  
Alton B. Horsfall
Keyword(s):  
Atomic Layer Deposition ◽  
Gate Dielectric ◽  
Atomic Layer ◽  
Oxide Semiconductor ◽  
Mos Capacitors ◽  
Mos Capacitor ◽  
3 Dimensional ◽  
Layer Deposition ◽  
Show Evidence ◽  
Flatband Voltage

3-Dimensional 4H-SiC metal-oxide-semiconductor capacitors have been fabricated to determine the effect of the sidewall on the characteristics of 3-Dimentional gate structures. Al2O3 deposited by Atomic Layer Deposition (ALD) was used as the gate dielectric layer on the trench structure. The 3-D MOS capacitors exhibit increasing accumulation capacitance with excellent linearity as the sidewall area increases, indicating that ALD results in a highly conformal dielectric film. The capacitance – voltage characteristics also show evidence of a second flatband voltage, located at a higher bias than that seen for purely planar devices on the same sample. We also observe that the oxide capacitance of planar and 3-D MOS capacitors increases with temperature. Finally, we have found that the 3-D MOS capacitor has a weaker temperature dependence of flatband voltage in comparison to the conventional planar MOS capacitor due to the incorporation of the (1120) plane in the sidewall.

On Separating Oxide Charges and Interface Charges in 4H-SiC Metal-Oxide-Semiconductor Devices

2006 ◽  
Vol 527-529 ◽  
pp. 1007-1010 ◽  
Author(s):  
Daniel B. Habersat ◽  
Aivars J. Lelis ◽  
G. Lopez ◽  
J.M. McGarrity ◽  
F. Barry McLean
Keyword(s):  
Room Temperature ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Interface Traps ◽  
Mos Capacitors ◽  
Mos Devices ◽  
Interface Charges ◽  
Flatband Voltage ◽  
Oxide Traps ◽  
P Type

We have investigated the distribution of oxide traps and interface traps in 4H Silicon Carbide MOS devices. The density of interface traps, Dit, was characterized using standard C-V techniques on capacitors and charge pumping on MOSFETs. The number of oxide traps, NOT, was then calculated by measuring the flatband voltage VFB in p-type MOS capacitors. The amount that the measured flatband voltage shifts from ideal, minus the contributions due to the number of filled interface traps Nit, gives an estimate for the number of oxide charges present. We found Dit to be in the low 1011cm−2eV−1 range in midgap and approaching 1012 −1013cm−2eV−1 near the band edges. This corresponds to an Nit of roughly 2.5 ⋅1011cm−2 for a typical capacitor in flatband at room temperature. This data combined with measurements of VFB indicates the presence of roughly 1.3 ⋅1012cm−2 positive NOT charges in the oxide near the interface for our samples.

Optimization of 4H-SiC MOS Properties with Cesium Implantation

2008 ◽  
Vol 600-603 ◽  
pp. 751-754 ◽  
Author(s):  
Y. Wang ◽  
T. Khan ◽  
T. Paul Chow
Keyword(s):  
Low Frequency ◽  
Conduction Band Edge ◽  
Electrical Characteristics ◽  
Mos Capacitors ◽  
Oxide Charge ◽  
Charge Densities ◽  
Effective Oxide Charge ◽  
Flatband Voltage ◽  
State Densities ◽  
Interfacial State

The effect of incorporation of cesium with implantation on the electrical characteristics of SiO2/4H-SiC interface has been evaluated using MOS capacitors. With a cesium dosage of 1012 and 3x1012 cm-2 on deposited oxide re-oxidized in steam, effective oxide charge densities of - 1.4x1012 and -7.5x1011 cm-2 respectively were extracted and a cesium implant activation percentage of 33% was estimated from flatband voltage shift. Also, corresponding interfacial state densities of 2.5x1013 and 1.8x1013 cm-2-eV-1 near the conduction band edge were extracted from High-Low frequency C-V technique, showing a decreasing Dit with increasing Cs dosage.

Comparative Studies of Gate Oxides Using Thermal, Stacked Gate, and Rapid Thermal Oxidation

1990 ◽  
Vol 182 ◽  
Author(s):  
S. Chittipeddi ◽  
P. K. Roy ◽  
V. C. Kannan ◽  
R. Singh ◽  
C. M. Dziuba
Keyword(s):  
Thermal Oxidation ◽  
Defect Density ◽  
Gate Oxide ◽  
Gate Oxides ◽  
Mos Capacitors ◽  
Rapid Thermal Oxidation ◽  
Transmission Electron ◽  
Lattice Images ◽  
Flatband Voltage

AbstractIn this paper we report on the quality of gate oxides obtained using three different oxidation techniques, namely thermal oxidation, rapid thermal oxidation and stacked gate oxidation. We report on the oxide thicknesses, the flatband voltage, threshold voltage, and QSS/Q values for MOS capacitors fabricated using these three techniques. We also fabricated MOSFET's using thermal oxides and stacked gate oxides, and find that the stacked gate oxides have a lower gate oxide defect density. Lattice images have also been obtained for the Si/SiO2 interface using transmission electron microscopy (TEM). We find that stacked oxide synthesis results in lower stresses and asperities at the interface relative to thermal and rapid thermal oxidation.

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