Effect of stacking order on device performance of bilayer black phosphorene-field-effect transistor

2015 ◽  
Vol 118 (22) ◽  
pp. 224501 ◽  
Author(s):  
A. Mukhopadhyay ◽  
L. Banerjee ◽  
A. Sengupta ◽  
H. Rahaman
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Device Performance ◽  
Stacking Order ◽  
Black Phosphorene ◽  
Effect Transistor

scholarly journals Growth and Device Performance of AlGaN/GaN Heterostructure with AlSiC Precoverage on Silicon Substrate

2014 ◽  
Vol 2014 ◽  
pp. 1-6
Author(s):  
Jae-Hoon Lee ◽  
Jung-Hee Lee
Keyword(s):  
Threshold Voltage ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Film Growth ◽  
Drain Current ◽  
Device Performance ◽  
Wetting Layer ◽  
Si Substrate ◽  
Effect Transistor ◽  
Gan Heterostructure

A crack-free AlGaN/GaN heterostructure was grown on 4-inch Si (111) substrate with initial dot-like AlSiC precoverage layer. It is believed that introducing the AlSiC layer between AlN wetting layer and Si substrate is more effective in obtaining a compressively stressed film growth than conventional Al precoverage on Si surface. The metal semiconductor field effect transistor (MESFET), fabricated on the AlGaN/GaN heterostructure grown with the AlSiC layer, exhibited normally on characteristics, such as threshold voltage of −2.3 V, maximum drain current of 370 mA/mm, and transconductance of 124 mS/mm.

Characterization of device performance and reliability of high performance Ge-on-Si field-effect transistor

2011 ◽  
Vol 88 (12) ◽  
pp. 3424-3427 ◽  
Author(s):  
Won-Ho Choi ◽  
Jungwoo Oh ◽  
Ook-Sang Yoo ◽  
In-Shik Han ◽  
Min-Ki Na ◽  
...  
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
Device Performance ◽  
Effect Transistor

Improving device performance of p-type organic field-effect transistor using butterfly like triarylamines

2020 ◽  
Vol 81 ◽  
pp. 105568 ◽  
Author(s):  
Ramachandran Dheepika ◽  
Anisha Shaji ◽  
Predhanekar Mohamed Imran ◽  
Samuthira Nagarajan
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Device Performance ◽  
Organic Field Effect Transistor ◽  
Effect Transistor ◽  
P Type

An Extensive Simulation Study of Gate Underlap Influence on Device Performance of Surrounding Gate In0.53Ga0.47As/InP Hetero Field Effect Transistor

2020 ◽  
Vol 10 (2) ◽  
pp. 157-165
Author(s):  
Soumya S. Mohanty ◽  
Urmila Bhanja ◽  
Guru P. Mishra
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Model Simulation ◽  
Drain Current ◽  
Oxide Semiconductor ◽  
Device Performance ◽  
Short Channel ◽  
Effect Transistor ◽  
Rf Performance ◽  
Gate Underlap

Background: This work describes the implementation of In0.53Ga0.47As/InP Surrounding Metal Gate Oxide Semiconductor Heterostructure Field Effect Transistor (SG MOSHFET) with gate underlap on both source and drain end to improve the DC and RF performance. Methods: A comprehensive and methodological investigation of DC and RF performance of III-V semiconductor are made for different underlap length varying from 5nm to 30nm on both sides of the device, which is used to mitigate the short channel issues to improve the device performance. Hydrodynamic model has been taken into consideration for the device simulation and it also includes Auger recombination and the Shockley–Read–Hall (SRH) model. Simulation is performed to analyze the various analog performance of device like drain current, surface potential, transconductance, threshold voltage, drain induced barrier lowering, off current, subthreshold slope, Ion/Ioff ratio, output conductance, intrinsic delay, energy-delay product, transconductance generation factor and radio frequency performance of device, like trans-frequency product and cut-off frequency. Results: From the simulation, it can be observed that an improved analog and RF performance is obtained at the optimum underlap length. Conclusion: This work delivers an idea for extended researchers to investigate different aspects of group III–V underlap MOSFETs.

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