Study of heat sources interacting in integrated circuits by laser mirage effect

2014 ◽  
Vol 105 (8) ◽  
pp. 084101 ◽  
Author(s):  
X. Perpiñà ◽  
X. Jordà ◽  
M. Vellvehi ◽  
J. Altet
2015 ◽  
Vol 112 (16) ◽  
pp. 4846-4851 ◽  
Author(s):  
Kathleen M. Hoogeboom-Pot ◽  
Jorge N. Hernandez-Charpak ◽  
Xiaokun Gu ◽  
Travis D. Frazer ◽  
Erik H. Anderson ◽  
...  

Understanding thermal transport from nanoscale heat sources is important for a fundamental description of energy flow in materials, as well as for many technological applications including thermal management in nanoelectronics and optoelectronics, thermoelectric devices, nanoenhanced photovoltaics, and nanoparticle-mediated thermal therapies. Thermal transport at the nanoscale is fundamentally different from that at the macroscale and is determined by the distribution of carrier mean free paths and energy dispersion in a material, the length scales of the heat sources, and the distance over which heat is transported. Past work has shown that Fourier’s law for heat conduction dramatically overpredicts the rate of heat dissipation from heat sources with dimensions smaller than the mean free path of the dominant heat-carrying phonons. In this work, we uncover a new regime of nanoscale thermal transport that dominates when the separation between nanoscale heat sources is small compared with the dominant phonon mean free paths. Surprisingly, the interaction of phonons originating from neighboring heat sources enables more efficient diffusive-like heat dissipation, even from nanoscale heat sources much smaller than the dominant phonon mean free paths. This finding suggests that thermal management in nanoscale systems including integrated circuits might not be as challenging as previously projected. Finally, we demonstrate a unique capability to extract differential conductivity as a function of phonon mean free path in materials, allowing the first (to our knowledge) experimental validation of predictions from the recently developed first-principles calculations.


2010 ◽  
Vol 35 (15) ◽  
pp. 2657 ◽  
Author(s):  
Xavier Perpiñà ◽  
Josep Altet ◽  
Xavier Jordà ◽  
Miquel Vellvehi ◽  
Narcís Mestres

Sensors ◽  
2020 ◽  
Vol 20 (5) ◽  
pp. 1446 ◽  
Author(s):  
Kodai Matsuhashi ◽  
Toshiki Kanamoto ◽  
Atsushi Kurokawa

The market for wearable devices such as smart watches and smart glasses continues to grow rapidly. Smart glasses are attracting particular attention because they offer convenient features such as hands-free augmented reality (AR). Since smart glasses directly touch the face and head, the device with high temperature has a detrimental effect on human physical health. This paper presents a thermal network model in a steady state condition and thermal countermeasure methods for thermal management of future smart glasses. It is accomplished by disassembling the state by wearing smart glasses into some parts, creating the equivalent thermal resistance circuit for each part, approximating heat-generating components such as integrated circuits (ICs) to simple physical structures, setting power consumption to the heat sources, and providing heat transfer coefficients of natural convection in air. The average temperature difference between the thermal network model and a commercial thermal solver is 0.9 °C when the maximum temperature is 62 °C. Results of an experiment using the model show that the temperature of the part near the ear that directly touches the skin can be reduced by 51.4% by distributing heat sources into both sides, 11.1% by placing higher heat-generating components farther from the ear, and 65.3% in comparison with all high conductivity materials by using a combination of low thermal conductivity materials for temples and temple tips and high conductivity materials for rims.


Author(s):  
Simon Thomas

Trends in the technology development of very large scale integrated circuits (VLSI) have been in the direction of higher density of components with smaller dimensions. The scaling down of device dimensions has been not only laterally but also in depth. Such efforts in miniaturization bring with them new developments in materials and processing. Successful implementation of these efforts is, to a large extent, dependent on the proper understanding of the material properties, process technologies and reliability issues, through adequate analytical studies. The analytical instrumentation technology has, fortunately, kept pace with the basic requirements of devices with lateral dimensions in the micron/ submicron range and depths of the order of nonometers. Often, newer analytical techniques have emerged or the more conventional techniques have been adapted to meet the more stringent requirements. As such, a variety of analytical techniques are available today to aid an analyst in the efforts of VLSI process evaluation. Generally such analytical efforts are divided into the characterization of materials, evaluation of processing steps and the analysis of failures.


Author(s):  
L.J. Chen ◽  
Y.F. Hsieh

One measure of the maturity of a device technology is the ease and reliability of applying contact metallurgy. Compared to metal contact of silicon, the status of GaAs metallization is still at its primitive stage. With the advent of GaAs MESFET and integrated circuits, very stringent requirements were placed on their metal contacts. During the past few years, extensive researches have been conducted in the area of Au-Ge-Ni in order to lower contact resistances and improve uniformity. In this paper, we report the results of TEM study of interfacial reactions between Ni and GaAs as part of the attempt to understand the role of nickel in Au-Ge-Ni contact of GaAs.N-type, Si-doped, (001) oriented GaAs wafers, 15 mil in thickness, were grown by gradient-freeze method. Nickel thin films, 300Å in thickness, were e-gun deposited on GaAs wafers. The samples were then annealed in dry N2 in a 3-zone diffusion furnace at temperatures 200°C - 600°C for 5-180 minutes. Thin foils for TEM examinations were prepared by chemical polishing from the GaA.s side. TEM investigations were performed with JE0L- 100B and JE0L-200CX electron microscopes.


Author(s):  
E.D. Wolf

Most microelectronics devices and circuits operate faster, consume less power, execute more functions and cost less per circuit function when the feature-sizes internal to the devices and circuits are made smaller. This is part of the stimulus for the Very High-Speed Integrated Circuits (VHSIC) program. There is also a need for smaller, more sensitive sensors in a wide range of disciplines that includes electrochemistry, neurophysiology and ultra-high pressure solid state research. There is often fundamental new science (and sometimes new technology) to be revealed (and used) when a basic parameter such as size is extended to new dimensions, as is evident at the two extremes of smallness and largeness, high energy particle physics and cosmology, respectively. However, there is also a very important intermediate domain of size that spans from the diameter of a small cluster of atoms up to near one micrometer which may also have just as profound effects on society as “big” physics.


Author(s):  
John R. Devaney

Occasionally in history, an event may occur which has a profound influence on a technology. Such an event occurred when the scanning electron microscope became commercially available to industry in the mid 60's. Semiconductors were being increasingly used in high-reliability space and military applications both because of their small volume but, also, because of their inherent reliability. However, they did fail, both early in life and sometimes in middle or old age. Why they failed and how to prevent failure or prolong “useful life” was a worry which resulted in a blossoming of sophisticated failure analysis laboratories across the country. By 1966, the ability to build small structure integrated circuits was forging well ahead of techniques available to dissect and analyze these same failures. The arrival of the scanning electron microscope gave these analysts a new insight into failure mechanisms.


Author(s):  
N. Rozhanski ◽  
V. Lifshitz

Thin films of amorphous Ni-Nb alloys are of interest since they can be used as diffusion barriers for integrated circuits on Si. A native SiO2 layer is an effective barrier for Ni diffusion but it deformation during the crystallization of the alloy film lead to the appearence of diffusion fluxes through it and the following formation of silicides. This study concerns the direct evidence of the action of stresses in the process of the crystallization of Ni-Nb films on Si and the structure of forming NiSi2 islands.


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