This paper presents the design analysis of Dynamic Random Access Memory (DRAM) with one transistor one diode (1T1D). The proposed structure consists of one transistor and one voltage controlled diode capacitor. The word and bit lines are connected with two voltage sources for the write
operation. The source and drain of the NMOS is tied together to form the diode structure. The off-state leakage current is the main cause for the power dissipation of DRAM. Thus the improvement of power efficiency to the overall system is a critical task. The conventional DRAM cell contains
one capacitor and one transistor. But the absence of capacitor in the proposed work is advantageous by means of compatibility, scalability, fabrication complexity, and cost. Tanner EDA working platform of 7 nm technology is used for the implementation of 1T1D DRAM cell in proposed work. This
work achieve the power dissipation, read and write access time in the range of 2.647 mW, 0.04 μs and 0.021 μs respectively. Also, the parameter comparison is performed by changing the technologies from 10 nm to 20 nm for 1T1D DRAM cell design.
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