Measurement ofn‐type dry thermally oxidized 6H‐SiC metal‐oxide‐semiconductor diodes by quasistatic and high‐frequency capacitance versus voltage and capacitance transient techniques

1994 ◽  
Vol 75 (12) ◽  
pp. 7949-7953 ◽  
Author(s):  
P. Neudeck ◽  
S. Kang ◽  
J. Petit ◽  
M. Tabib‐Azar
MRS Advances ◽  
2017 ◽  
Vol 2 (02) ◽  
pp. 103-108 ◽  
Author(s):  
Yanbin An ◽  
Aniruddh Shekhawat ◽  
Ashkan Behnam ◽  
Eric Pop ◽  
Ant Ural

ABSTRACT We fabricate and characterize metal-oxide-semiconductor (MOS) devices with graphene as the gate electrode, 5 or 10 nm thick silicon dioxide as the insulator, and silicon as the semiconductor substrate. We find that Fowler-Nordheim tunneling dominates the gate current for the 10 nm oxide device. We also study the temperature dependence of the tunneling current in these devices in the range 77 to 300 K and extract the effective tunneling barrier height as a function of temperature for the 10 nm oxide device. Furthermore, by performing high frequency capacitance-voltage measurements, we observe a local capacitance minimum under accumulation, particularly for the 5 nm oxide device. By fitting the data using numerical simulations based on the modified density of states of graphene in the presence of charged impurities, we show that this local minimum results from the quantum capacitance of graphene. These results provide important insights for the heterogeneous integration of graphene into conventional silicon technology.


2007 ◽  
Vol 101 (12) ◽  
pp. 124501 ◽  
Author(s):  
Reza Navid ◽  
Christoph Jungemann ◽  
Thomas H. Lee ◽  
Robert W. Dutton

2019 ◽  
Vol 963 ◽  
pp. 240-243
Author(s):  
Yusuke Yamashita

To identify the near-interface trap (NIT) distribution of a metal oxide semiconductor (MOS) capacitor, we propose a new evaluation method by parameter estimation through optimization. The MOS capacitor was fabricated with Al/SiO2 (75 nm)/SiC and measured by the capacitance transient (C-t) method. In addition, C-t signals were calculated from the assumed NIT distribution model. Then, the calculated C-t signals were modified to fit the measured signals by optimization of the parameters of the NIT model. The two types of NITs, deep (Ec – Et = 0.57 eV) and shallow (Ec – Et = -0.02 eV or-0.18 eV), were revealed by this method.


Electronics ◽  
2020 ◽  
Vol 9 (7) ◽  
pp. 1089
Author(s):  
Fabrizio Palma

The use of a metal–oxide–semiconductor field-effect transistor (MOS-FET) permits the rectification of electromagnetic radiation by employing integrated circuit technology. However, obtaining a high-efficiency rectification device requires the assessment of a physical model capable of providing a qualitative and quantitative explanation of the processes involved. For a long time, high-frequency detection based on MOS technology was explained using plasma wave detection theory. In this paper, we review the rectification mechanism in light of high-frequency numerical simulations, showing features never examined until now. The results achieved substantially change our understanding of terahertz (THz) rectification in semiconductors, and can be interpreted by the model based on the self-mixing process in the device substrate, providing a new and essential tool for designing this type of detector.


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