Influence of polysilicon gate formation conditions on thin gate oxide (4–6 nm) dielectric and charging properties

1993 ◽  
Vol 73 (11) ◽  
pp. 7515-7519 ◽  
Author(s):  
Manabu Itsumi ◽  
Noboru Shiono ◽  
Masakazu Shimaya
1995 ◽  
Vol 16 (11) ◽  
pp. 470-472 ◽  
Author(s):  
Chao Sung Lai ◽  
Tan Fu Lei ◽  
Chune Len Lee ◽  
Tien Sheng Chao

2002 ◽  
Vol 46 (2) ◽  
pp. 243-247 ◽  
Author(s):  
Chew-Hoe Ang ◽  
Lian-Hoon Ko ◽  
Wenhe Lin ◽  
Jia-Zhen Zheng

1995 ◽  
Vol 142 (8) ◽  
pp. 2786-2789 ◽  
Author(s):  
Kunihiro Suzuki ◽  
Akira Satoh ◽  
Takayuki Aoyama ◽  
Itaru Namura ◽  
Fumihiko Inoue ◽  
...  

Author(s):  
N. David Theodore ◽  
Merit Hung

Silicon device-technology makes extensive use of polysilicon layers for capacitors, contact-materials, thin-film diodes, transistors and resistors. In metal-oxide-semiconductor field-effect transistors (MOSFETs) polysilicon is used as the gate electrode on top of a thin gate-oxide layer. The microstructure and stability of the polysilicon and gate-oxide layers can strongly influence electrical behavior of the transistors. Any microstructural deterioration that occurs as a result of processing can result in reduced charge-to-breakdown and lowered breakdown voltages. It is known that interfacial oxides inadvertently present at interfaces of silicon/polysilicon structures break-up as the structures are annealed, Whereas agglomeration of oxide is beneficial in some structures, in MOSFETs such deterioration would be disastrous. The stability of polysilicon/ gate-oxide structures for various processing conditions likely to be used during device-fabrication needs to be characterized. The present study investigates the thermal stability of polysilicon gate-electrode/ gate-oxide structures annealed in a hydrogen ambient at temperatures varying from 800°C to 1050°C.


1999 ◽  
Vol 592 ◽  
Author(s):  
Siguang Ma ◽  
Yaohui Zhang ◽  
M. F. Li ◽  
Weidan Li ◽  
J. L. F. Wang ◽  
...  

ABSTRACTIn this paper we carefully investigate the correlation between gate induced drain leakage current and plasma induced damages in the deep submicron p+ polysilicon gate pMOSFETs with gate oxide thickness of 50 Å. Low field enhancement of gate induced drain leakage current caused by plasma charging damage is a function of metal 1 antenna area/length ratio and cell location. Combined with the charge pumping measurements, it is found that gate induced drain leakage current enhancement is mainly due to the plasma induced interface traps. A linear relationship between the gate induced drain leakage and the plasma induced interface trap density is observed within the experimental error. On the other hand, the threshold voltage measurements show that oxide trapped charge has no major contribution to, and no correlation with, the gate induced drain leakage current for thin gate oxide MOSFET devices.


2002 ◽  
Vol 12 (3) ◽  
pp. 57-60 ◽  
Author(s):  
B. Cretu ◽  
F. Balestra ◽  
G. Ghibaudo ◽  
G. Guégan

2009 ◽  
Vol 30 (1) ◽  
pp. 014004 ◽  
Author(s):  
Liu Mengxin ◽  
Han Zhengsheng ◽  
Bi Jinshun ◽  
Fan Xuemei ◽  
Liu Gang ◽  
...  

Sign in / Sign up

Export Citation Format

Share Document