Monte Carlo modeling of electron transport in a Si metal‐oxide‐semiconductor inversion layer including quantum state and bulk scattering

1991 ◽  
Vol 70 (3) ◽  
pp. 1522-1530 ◽  
Author(s):  
Syunji Imanaga ◽  
Yoshinori Hayafuji
Keyword(s):  
Monte Carlo ◽  
Electron Transport ◽  
Metal Oxide ◽  
Quantum State ◽  
Inversion Layer ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Monte Carlo Modeling ◽  
Bulk Scattering

Suppression of Timing Variations due to Random Dopant Fluctuation by Back-Gate Bias in a Nanometer CMOS Inverter

2020 ◽  
Vol 13 ◽  
Author(s):  
Kai Zhang ◽  
Weifeng Lü ◽  
Peng Si ◽  
Zhifeng Zhao ◽  
Tianyu Yu
Keyword(s):  
Monte Carlo ◽  
Integrated Circuits ◽  
Metal Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Cmos Inverter ◽  
Back Gate ◽  
Random Dopant Fluctuation ◽  
Random Dopant

Background: In state-of-the-art nanometer metal-oxide-semiconductor-field-effect- transistors (MOSFETs), optimization of timing characteristic is one of the major concerns in the design of modern digital integrated circuits. Objective: This study proposes an effective back-gate-biasing technique to comprehensively investigate the timing and its variation due to random dopant fluctuation (RDF) employing Monte Carlo methodology. Methods: To analyze RDF-induced timing variation in a 22-nm complementary metal-oxide semiconductor (CMOS) inverter, an ensemble of 1000 different samples of channel-doping for negative metal-oxide semiconductor (NMOS) and positive metal-oxide semiconductor (PMOS) was reproduced and the input/output curves were measured. Since back-gate bias is technology dependent, we present in parallel results with and without VBG. Results: It is found that the suppression of RDF-induced timing variations can be achieved by appropriately adopting back-gate voltage (VBG) through measurements and detailed Monte Carlo simulations. Consequently, the timing parameters and their variations are reduced and, moreover, that they are also insensitive to channel doping with back-gate bias. Conclusion: Circuit designers can appropriately use back-gate bias to minimize timing variations and improve the performance of CMOS integrated circuits.

Improving the accuracy of the charge-sheet model for the long-channel metal-oxide semiconductor field-effect transistor

1987 ◽  
Vol 65 (8) ◽  
pp. 995-998
Author(s):  
N. G. Tarr
Keyword(s):  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Inversion Layer ◽  
Potential Drop ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Analytic Approximation ◽  
Effect Transistor ◽  
Long Channel

It is shown that the accuracy of the charge-sheet model for the long-channel metal-oxide-semiconductor field-effect transistor can be improved by allowing for the small potential drop across the inversion layer, and by using a more accurate analytic approximation for the charge stored in the depletion region.

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