The influence of Fermi level pinning/depinning on the Schottky barrier height and contact resistance in Ge/CoFeB and Ge/MgO/CoFeB structures

2010 ◽  
Vol 96 (5) ◽  
pp. 052514 ◽  
Author(s):  
Donkoun Lee ◽  
Shyam Raghunathan ◽  
Robert J. Wilson ◽  
Dmitri E. Nikonov ◽  
Krishna Saraswat ◽  
...  
Keyword(s):  
Contact Resistance ◽  
Fermi Level ◽  
Schottky Barrier ◽  
Barrier Height ◽  
Schottky Barrier Height ◽  
Fermi Level Pinning

scholarly journals Reduction of Schottky Barrier Height at Graphene/Germanium Interface with Surface Passivation

2019 ◽  
Vol 9 (23) ◽  
pp. 5014
Author(s):  
Courtin ◽  
Moréac ◽  
Delhaye ◽  
Lépine ◽  
Tricot ◽  
...  
Keyword(s):  
Fermi Level ◽  
Schottky Barrier ◽  
Barrier Height ◽  
Schottky Barrier Height ◽  
Surface Passivation ◽  
2D Materials ◽  
Semiconductor Interface ◽  
Weakly Interact ◽  
Fermi Level Pinning ◽  
Semiconductor Interfaces

Fermi level pinning at metal/semiconductor interfaces forbids a total control over the Schottky barrier height. 2D materials may be an interesting route to circumvent this problem. As they weakly interact with their substrate through Van der Waals forces, deposition of 2D materials avoids the formation of the large density of state at the semiconductor interface often responsible for Fermi level pinning. Here, we demonstrate the possibility to alleviate Fermi-level pinning and reduce the Schottky barrier height by the association of surface passivation of germanium with the deposition of 2D graphene.

Increase in Schottky Barrier Height in the CoSi2/Si (100) Interface Caused by Hydrogen

1992 ◽  
Vol 281 ◽  
Author(s):  
A. D. Marwick ◽  
M. O. Aboelfotoh ◽  
R. Casparis
Keyword(s):  
Fermi Level ◽  
Schottky Barrier ◽  
Barrier Height ◽  
Schottky Barrier Height ◽  
Interface States ◽  
Hydrogen Atoms ◽  
Fermi Level Pinning ◽  
Gap States

ABSTRACTIt is shown that the presence of 8 × 1015 hydrogen atoms/cm2 in the CoSi2/Si (100) interface causes an increase in the Schottky barrier height of 120 meV, and that passivation of dopants in the substrate is not the cause of this change. The data is evidence that the position of the Fermi level in this interface is controlled by defect-related interface states. After hydrogenation the Schottky barrier height agrees with that predicted by theory for Fermi level pinning by virtual gap states of the silicon.

Ultimately Low Schottky Barrier Height at NiSi/Si Junction by Sulfur Implantation after Silicidation for Aggressive Scaling of MOSFETs

2009 ◽  
Vol 1155 ◽  
Author(s):  
Yen-Chu Yang ◽  
Yoshifumi Nishi ◽  
Atsuhiro Kinoshita
Keyword(s):  
Contact Resistance ◽  
Schottky Barrier ◽  
Barrier Height ◽  
Schottky Barrier Height ◽  
Nickel Silicide ◽  
High Concentration ◽  
Cross Sectional ◽  
Deep Impurity ◽  
Fermi Level Pinning ◽  
Parasitic Resistance

AbstractParasitic resistance, particularly source/drain contact resistance becomes one of the most serious problems to extend MOSFET scaling recently. Nickel silicide (NiSi), with advantages of low resistivity and high scalability, has been chosen as the material for source/drain formation. However, its Schottky barrier height (SBH) of 0.65eV for electrons is so high that it would block electrons from tunneling, therefore becomes an obstacle to further reduce the contact resistance, which is necessary to achieve the future scaling. Among several solutions, high concentration impurity-segregation layers have been introduced at NiSi/Si interfaces to reduce SBH of MS-MOSFETs. Sulfur (S) has been considered to be an efficient material for the segregation-layer to reduce SBH owing to Fermi-level pinning effect. Previous studies have investigated segregation by implanting S before NiSi formation. Because of the high diffusivity of S in Si, S profile becomes broad during silicidation process, which leads to loss of S concentration at the interface. Moreover, S ions spread into the substrate and channel region generate deep impurity levels that induce junction leakage and off leakage, resulting in device performance degradation. In this paper, S implantation after Ni silicidation is proposed to suppress S diffusion because NiSi is expected to be an efficient barrier for S diffusion. In addition, NiSi/Si interface can serve as a potential energetic valley which may trap S during thermal treatment after implantation. In this work, S was implanted into NiSi/n-Si diodes at the energy of 10keV with dose of 5�1014 and 1015 cm-3 after NiSi is formed. The projection range of S in NiSi is about 6nm, while thickness of NiSi is 16nm. Some devices were annealed at 300C and 450C. The I-V characteristics show that SBH is sufficiently reduced as the annealing temperature becomes higher, and it reaches as low as 3.4meV for 450C annealing. SBH of 3.4meV is much lower than the previously reported value of 70meV for which S was implanted before silicidation. The SIMS analysis result also proves the S profile is much sharper than having S-implantation before Ni silicidation, which supports our hypothesis that S diffusion is suppressed through our process and avoid the loss of S concentration at the interface. Moreover, despite the worry that S-implantation might damage the NiSi/Si interface morphology, cross sectional TEM images show that the interfacial flatness is completely the same as that of non-implanted NiSi/Si, indicating that no degradation occurs by S implantation. In summary, S-implantation after NiSi formation, which provides ultimately low SBH at NiSi/Si interface, is a promising technique to realize ultra-low parasitic resistance source/drain for future LSI beyond 16nm generation.

Temperature dependent Schottky barrier height and Fermi level pinning on Au/HBC/GaAs diodes

2008 ◽  
Vol 92 (15) ◽  
pp. 153309 ◽  
Author(s):  
Soner Özcan ◽  
Jürgen Smoliner ◽  
Thomas Dienel ◽  
Torsten Fritz
Keyword(s):  
Fermi Level ◽  
Schottky Barrier ◽  
Barrier Height ◽  
Schottky Barrier Height ◽  
Temperature Dependent ◽  
Fermi Level Pinning

SCHOTTKY BARRIER HEIGHT AND ATOMIC STRUCTURE OF EPITAXIAL Pb/Si(111) INTERFACES

1991 ◽  
Vol 05 (06) ◽  
pp. 397-405
Author(s):  
D.R. HESLINGA ◽  
T.M. KLAPWIJK ◽  
H.H. WEITERING ◽  
T. HIBMA
Keyword(s):  
Electrical Properties ◽  
Fermi Level ◽  
Schottky Barrier ◽  
Barrier Height ◽  
Atomic Structure ◽  
Schottky Barrier Height ◽  
Interface State ◽  
The Other ◽  
Fermi Level Pinning ◽  
Structural And Electrical Properties

We review experiments on epitaxial Pb/Si (111) interfaces. Emphasis is laid on the interplay between structural and electrical properties, in particular the relation of the Schottky barrier height (SBH) with the structure of the first monoatomic Pb adlayer. Two structures can be formed, which differ only in the arrangement of the first layer of Pb and Si atoms at the interface. One, a Si (111)(7×7)- Pb structure, has a SBH of 0.70 eV. The other, a Si (111)(√3×√3) R 30°- Pb structure has a SBH of 0.93 eV. Angle resolved photoemission results favor an interpretation in terms of Fermi level pinning by a discrete locali::ed interface state.

scholarly journals Oxidized-monolayer tunneling barrier for strong Fermi-level depinning in layered InSe transistors

2019 ◽  
Vol 3 (1) ◽  
Author(s):  
Yi-Hsun Chen ◽  
Chih-Yi Cheng ◽  
Shao-Yu Chen ◽  
Jan Sebastian Dominic Rodriguez ◽  
Han-Ting Liao ◽  
...  
Keyword(s):  
Fermi Level ◽  
Schottky Barrier ◽  
Barrier Height ◽  
Schottky Barrier Height ◽  
Field Effect Transistors ◽  
High Mobility ◽  
Surface Oxidation ◽  
Tunneling Barrier ◽  
Experimental Realization ◽  
Gap States

AbstractIn two-dimensional (2D)-semiconductor-based field-effect transistors and optoelectronic devices, metal–semiconductor junctions are one of the crucial factors determining device performance. The Fermi-level (FL) pinning effect, which commonly caused by interfacial gap states, severely limits the tunability of junction characteristics, including barrier height and contact resistance. A tunneling contact scheme has been suggested to address the FL pinning issue in metal–2D-semiconductor junctions, whereas the experimental realization is still elusive. Here, we show that an oxidized-monolayer-enabled tunneling barrier can realize a pronounced FL depinning in indium selenide (InSe) transistors, exhibiting a large pinning factor of 0.5 and a highly modulated Schottky barrier height. The FL depinning can be attributed to the suppression of metal- and disorder-induced gap states as a result of the high-quality tunneling contacts. Structural characterizations indicate uniform and atomically thin-surface oxidation layer inherent from nature of van der Waals materials and atomically sharp oxide–2D-semiconductor interfaces. Moreover, by effectively lowering the Schottky barrier height, we achieve an electron mobility of 2160 cm2/Vs and a contact barrier of 65 meV in two-terminal InSe transistors. The realization of strong FL depinning in high-mobility InSe transistors with the oxidized-monolayer presents a viable strategy to exploit layered semiconductors in contact engineering for advanced electronics and optoelectronics.

Contact Resistance Reduction to FinFET Source/Drain Using Novel Dielectric Dipole Schottky Barrier Height Modulation Method

2011 ◽  
Vol 32 (7) ◽  
pp. 862-864 ◽  
Author(s):  
Brian E. Coss ◽  
Casey Smith ◽  
Wei-Yip Loh ◽  
Prashant Majhi ◽  
Robert M. Wallace ◽  
...  
Keyword(s):  
Contact Resistance ◽  
Schottky Barrier ◽  
Barrier Height ◽  
Schottky Barrier Height ◽  
Modulation Method ◽  
Resistance Reduction
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