ABSTRACTSiC is suitable for power devices but high quality SiC epitaxial layers having a high breakdown voltage are needed and thick epilayer is indispensable. In this study, CST method (Close Space Technique) was used to rapidly grow thick epitaxial layers. Source material used was 3C-SiC polycrystalline plate of high purity while 4H-SiC(0001) crystals inclined 8° off toward <1120> was used for the substrate. Quality of the epilayer was influenced significantly by pressure during growth and polarity of the substrate. A p-type conduction was obtained by changing the size of p-type source material. The carrier concentration of epilayer decreased when a lower pressure was employed. Schottky diode was also fabricated.
First-principles study on intrinsic defects of SnSe