The complex evolution of strain during nanoscale patterning of 60 nm thick strained silicon layer directly on insulator

2009 ◽  
Vol 94 (24) ◽  
pp. 243113 ◽  
Author(s):  
O. Moutanabbir ◽  
M. Reiche ◽  
W. Erfurth ◽  
F. Naumann ◽  
M. Petzold ◽  
...  
Keyword(s):  
Silicon Layer ◽  
Strained Silicon ◽  
Nanoscale Patterning

ANALYSIS OF THE EFFECTS OF STRAIN IN ULTRA-THIN SOI MOS DEVICES

2006 ◽  
Vol 16 (01) ◽  
pp. 105-114
Author(s):  
NICOLA BARIN ◽  
CLAUDIO FIEGNA ◽  
ENRICO SANGIORGI
Keyword(s):  
Silicon Layer ◽  
Tunneling Current ◽  
Thin Body ◽  
Strained Silicon ◽  
Carrier Distribution ◽  
Charge Voltage ◽  
Gate Electrodes ◽  
Poisson Equations ◽  
Mos Devices ◽  
Device Architecture

Ultra-thin body Double Gate MOS structures with strained silicon are investigated by solving the 1-D Schrödinger and Poisson equations, with open boundaries conditions on the wave functions in the gate electrodes. The electrostatics of this device architecture and its dependence on the amount of strain and on the thickness of the silicon layer is analyzed in terms of subband structure, subband population, carrier distribution within the strained-silicon layer, charge-voltage characteristics and gate tunneling current.

The electronic structure peculiarities of a strained silicon layer in silicon-on-insulator: Experimental and theoretical data

2016 ◽  
Vol 382 ◽  
pp. 331-335
Author(s):  
V.A. Terekhov ◽  
D.N. Nesterov ◽  
E.P. Domashevskaya ◽  
E.V. Geraskina ◽  
M.D. Manyakin ◽  
...  
Keyword(s):  
Electronic Structure ◽  
Silicon Layer ◽  
Theoretical Data ◽  
Silicon On Insulator ◽  
Strained Silicon

μMAX Enhanced 190% of a Strained NMOS Based on SiGe Virtual Substrate

2013 ◽  
Vol 756-759 ◽  
pp. 154-157
Author(s):  
Zhao Huan Tang ◽  
Kai Zhou Tan ◽  
Wei Cui ◽  
Bin Wang
Keyword(s):  
High Performance ◽  
Silicon Layer ◽  
Sige Layer ◽  
Strained Silicon ◽  
Low Field ◽  
Source Current ◽  
Maximal Mobility ◽  
Better Than ◽  
Strained Sige

Based on SiGe virtual substrate technology, a high-performance strained NMOS is obtained. By growing 2~3μm SiGe relaxed layer, 100~200nm strained SiGe layer and 20nm strained silicon layer, and also forming a P-well by multiple implantation technology, a surface strained NMOS is fabricated. Finally, Measured results shown that drain-source current and the low field maximal mobility of the strained NMOS are enhancement of up to 190% at Vgs=3.5V, which is almost three times to the value of common Silicon NMOS and is also better than the 170% reported in public.

Ab-Initio Study of Neutral Indium Diffusion in Uniaxially- and Biaxially-Strained Silicon

2008 ◽  
Vol 8 (9) ◽  
pp. 4565-4568
Author(s):  
Young-Kyu Kim ◽  
Bum-Goo Cho ◽  
Soon-Yeol Park ◽  
Taeyoung Won
Keyword(s):  
Ab Initio ◽  
Minimum Energy ◽  
Silicon Layer ◽  
Strained Silicon ◽  
Energy Structure ◽  
Migration Energy ◽  
Elastic Band ◽  
Tetrahedral Position ◽  
Substitutional Site ◽  
Indium Diffusion

In this paper, we present our ab-initio study on energy configurations, minimum energy path (MEP), and migration energy for neutral indium diffusion in a uniaxial and biaxial tensile strained {100} silicon layer. Our ab-initio calculation of the electronic structure allowed us to figure out transient atomistic configurations during the indium diffusion in strained silicon. We found that the lowest-energy structure (Ins – SiiTd) consists of indium sitting on a substitutional site while stabilizing a silicon self-interstitial in a nearby tetrahedral position. Our ab-initio calculation implied that the next lowest energy structure is IniTd, the interstitial indium at the tetrahedral position. We employed the nudged elastic band (NEB) method for estimating the MEP between the two structures. The NEB method allowed us to find that that diffusion pathway of neutral indium is kept unchanged in strained silicon while the migration energy of indium fluctuates in strained silicon.

Thickness dependence of photoluminescence for tensely strained silicon layer on insulator

2008 ◽  
Vol 93 (19) ◽  
pp. 191913 ◽  
Author(s):  
J. Munguía ◽  
J-M. Bluet ◽  
M. Baira ◽  
O. Marty ◽  
G. Bremond ◽  
...  
Keyword(s):  
Silicon Layer ◽  
Thickness Dependence ◽  
Strained Silicon

Dielectric function of biaxially strained silicon layer

1996 ◽  
Vol 68 (22) ◽  
pp. 3153-3155 ◽  
Author(s):  
Hosun Lee ◽  
E. D. Jones
Keyword(s):  
Dielectric Function ◽  
Silicon Layer ◽  
Strained Silicon

Thermal Transport in Novel Silicon Transistors

2004 ◽  
Author(s):  
Keivan Etessam-Yazdani ◽  
Wenjun Liu ◽  
Yizhang Yang ◽  
Mehdi Asheghi
Keyword(s):  
Thermal Conductivity ◽  
Semiconductor Device ◽  
Silicon Layer ◽  
Phonon Transport ◽  
Interface Roughness ◽  
Strained Silicon ◽  
Boltzmann Transport ◽  
Strained Si ◽  
Thin Silicon ◽  
The Impact

This manuscript investigates the relevance and impact of nanoscale thermal phenomena in the state-of-the-art semiconductor device technologies such as: silicon-on-insulator (SOI), strained silicon, and tri-gate CMOS transistors. The experimental data and predictions for thin silicon layer thermal conductivity and the solutions of the Boltzmann transport equations (BTE) for phonon transport in strained-Si/Ge bi-layer configuration are used to estimate the thermal resistance of the SOI, tri-gate, and strained-silicon-on-SiGe-on-insulator (SGOI) transistors, respectively. In particular, the impact of SiGe underlayer and interface roughness on the lateral thermal conductivity of the silicon layer at room temperature is investigated. In order to avoid the complexity of the BTE for predictions of the temperature distribution, Lumped Analytical (LA) models are introduced that are simple to implement and also adequate enough to capture the sub-continuum effects. It is concluded that the SOI, SGOI and tri-gate transistors are all susceptible to self-heating for very thin silicon device layers.

Analysis of CMOS Logic Inverter Based on Gate-All-Around Field-Effect Transistors with the Strained-Silicon Layer for Improving the Switching Performances

2020 ◽  
Vol 20 (11) ◽  
pp. 6632-6637
Author(s):  
Sang Ho Lee ◽  
Min Su Cho ◽  
Jun Hyeok Jung ◽  
Won Douk Jang ◽  
Hye Jin Mun ◽  
...  
Keyword(s):  
Silicon Germanium ◽  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Silicon Layer ◽  
Strained Silicon ◽  
Core Shell ◽  
Operating Voltage ◽  
Electrical Characteristics ◽  
The Core

In this paper, we adopt the vertical core–shell nanowire field-effect transistors based on the Silicon-germanium (SiGe)/strained-silicon (strained-Si) layer as a method to improve the performance of the CMOS logic inverter by using technology computer aided design simulation. The lattice constant mismatch between the core region and the shell region causes the global strain of the Si region of the shell, which in turn changes the Si parameters. This phenomenon effects on the improvement the electrical characteristics in the p-type MOSFET (pMOSFET). Through this variation, the asymmetry of the electrical characteristics between n-type MOSFET (nMOSFET) and pMOSFET nanowire is considerably compensated. The inverter using the proposed core–shell structure shows the improved CMOS logic inverter characteristics. For example, the core–shell CMOS logic inverter shows performances such as NML = 0.315 V, NMH = 0.312 V, τPHL of 8.7 ps, and τPHL of 21 ps at an operating voltage of VDD = 0.7 V.

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